• Journal of the Korean Geotechnical Society
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• v.28 no.5
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• pp.109-120
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• 2012

In marine site surveys, drilling boreholes are restrictively conducted, while geophysical surveys are used with ease. To overcome the limitations of marine site survey, various site survey data should be collected and analysed by adopting complementary pros and cons. In this study, the integration assessment was established to digitize 2D geo-layer based on the overlapping of a few borehole data to seismic refraction tomography and to determine 3D geo-information based on the kriging for the design of offshore-foundation. And the overlapping method was proposed considering spatial variability of the tomography and separation distance from borehole position to determine the 2D geo-layer. Finally, the integration assessment was applied to offshore wind-turbine site in Jeju-do, and its applicability was verified based on the cross-validation.

• Journal of Advanced Navigation Technology
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• v.24 no.3
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• pp.184-191
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• 2020

Avionics System Integration Laboratory is the integrated test environment for integration and verification of avionics systems. When real equipment can not be used in the laboratory for various reasons, software models should be needed. Because there hasn't been any standardized method for the models so that it is difficult to reuse the developed models, the need for a framework to develop the avionics software models was emerged. We adopted DEVS(discrete event system specification) formalism as the standardized modeling method for the avionics software models. Due to DEVS formalism is based on event-driven algorithm, it doesn't accord a legacy system which has sequential and periodic algorithms. In this paper, we propose real-time event-driven modeling and simulation method for SIL to overcome these restrictions and to maximize reusability of avionics models through the analysis of the characteristics and the limitations of avionics models.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.69-77
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• 2016

We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with $80{\mu}m$ height is around 30 m for each pair of $10{\mu}m$ dia. electrode. Capacitance value of CNP bundle with $3{\mu}m$ length and $80{\mu}m$ height is around 0.6fF. Eye-diagram pattern shows no degradation even at 10Gbps data rate after the lamination of anisotropic conductive film.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.75-91
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• 2006

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.25-29
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• 2017

This paper presents a hetero-integration of electrostatically actuated RF MEMS Switch and step up DC-DC converter on a redistribution layer using commercial PCB process. RF characteristics of Duroid with $56{\Omega}$ impedance GCPW transmission line and that of FR4 with $59{\Omega}$ impedance CPW transmission line were analyzed. From DC to 6GHz, RF characteristics of Duroid were better than that of FR4, insertion loss was 2.08dB lower, return loss was 3.91dB higher, and isolation was 3.33dB higher.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Korean Management Science Review
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• v.25 no.3
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• pp.13-26
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• 2008

We investigate the effect of government and public sector R&D Investment at IT Industry on the amount of Production, export and nongovernment R&D Investment at IT Industry. We, firstly, examine the stationarity of each variable by the unit root t-test and perform the co-integration test for the pairs of variables. We use YECM(Vector Error Correction Model) according to the results of co-integration test for the examination of Granger-causality between variables. It is found that there exist an Granger-causality between public sector R&D Investment and nongovernment R&D investment and also between public sector R&D Investment and export. Secondly, we analyze the impulse response of government and public sector R&D Investment at IT Industry on the amount of production, export and nongovernment R&D investment at IT Industry based on VECM model. It is found that the response of the amount of production is highest at 3th period and is lowest at 8th period and that of export shows similar pattern.

• International Journal of CAD/CAM
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• v.6 no.1
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• pp.3-8
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• 2006

The application of three-dimensional (3-D) CAD has been popularized for design and production and digital manufacturing has been spreading in many industrial fields. By simulation of the production process using 3-D digital models, which are the core of CIM (Computer Integrated Manufacturing) system, the efficiency and safety of production are improved at each stage of work, and optimization of manufacturing can be achieved. This paper firstly describes the concept of "simulation based production" in shipbuilding and also digital manufacturing; the 3-D CAD system is indispensable for effective simulation because ship structure is three dimensionally complex. By simulation, "computer optimized manufacturing" can be possible. The most effective fields of simulation in shipbuilding are in jobs where many parties have to cooperate, while existing two-dimensional drawings are hardly observed the whole structures due to interference between structures or equipment of complex shape. In this paper some examples of the successful application in IHIMU (IHI Marine United Inc.) are shown: assembly of a pipe unit, erection of a complex hull block, carriage of equipment, installation of a propeller, and access in an engine room.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.12-22
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• 2021

Since the technical realization of self-aligned planar complementary metal-oxide-semiconductor field-effect transistors in 1960s, semiconductor manufacturing has aggressively pursued scaling that fruitfully resulted in tremendous advancement in device performances and realization of features sizes smaller than 10 nm. Due to many intrinsic material and technical obstacles, continuing the scaling progress of semiconductor devices has become increasingly arduous. As an effort to circumvent the areal limit, stacking devices in a three-dimensional fashion has been suggested. This approach is commonly called monolithic three-dimensional (M3D) integration. In this work, we examined technical issues that need to be addressed and overcome to fully realize energy efficiency, short latency and cost competency. Full-fledged M3D technologies are expected to contribute to various new fields of artificial intelligence, autonomous gadgets and unknowns, which are to be discovered.