• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.989-990
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• 2006

This paper presents a design of 3D Graphics Geometry processor. A geometry processor needs to cope with a large amount of computation and consists of transformation processor and lighting processor. To deal with the huge computation, a vector processing structure based on pipeline chaining is proposed. The proposed geometry processor performs 4.3M vertices/sec at 100MHz using 11 floating-point units.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.258-259
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• 2005

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• Journal of the Korea Computer Graphics Society
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• v.8 no.2
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• pp.31-38
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• 2002

This paper presents a method for real-time 3D Sumi-e rendering us ing normal graphics hardware. Sumi-e is one of the traditional oriental painting styles. Most research on Sumi-e paintings has focused on 2D or :2.5D Sumi-e brushwork simulation. On these systems. complicated user's hand drawing is required to generate the image of Sumi-e effects. and it can render the 2D or 2.5D Sumi-e images only. We present an automated rendering system for 3D image of Sumi-e painting. It uses 3D common object as an input data and does not need any additional input of user brushwork. Especially for the real-time rendering. hardware-accelerated algorithm for Sumi-e rendering is newly suggested in our system. It is designed with efficiency for customer level graphics hard ware. The results of this paper show that the features of traditional Sumi-e painting are successfully modeled and that 3D Sumi-e painting is rendered in real-time effectively.

• Journal of Digital Contents Society
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• v.8 no.2
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• pp.245-253
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• 2007

Recently, the use and application of computer graphics in the mobile and ubiquitous environment are growing. Real-time rendering and modeling for computer graphics are due to system performance, there're lots of limitation in lower system such as PDA and cell phone etc. Therefore, we suggested the intelligent Serving Rendering Middleware which is to provide adaptation service of computer graphics contents fit to user's environment real-time whatever environment the users are in. The Service Rendering Middleware needs multi-level configurations and applications, so, in this paper we propose multi-level algorithm to decide adaptation levels are deal with separately according to device performance.

• International Journal of CAD/CAM
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• v.3 no.1_2
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• pp.85-95
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• 2003

During the design of dies and molds, the cavity of the object is obtained by subtracting it from a surrounding rectangular block. This box is subsequently split into two halves by the parting surface. Similar problems also occur in some RP processes such as LOM, SGC, SLS and 3DP where the machine produces a block inside which the prototype is buried. Determining the orientation of the object inside the box and the corresponding parting surface taking appropriate constraints into account have been addressed by several researchers. However, given the parting surface, the problem of splitting the box development of a software package called OptiLOM (now a module of an RP software Magics 8.0), the authors realized non-triviality of this problem since the loop can spread over as many as 5 faces of the box. In this paper, the authors have tried to bring out the importance of this problem and have presented their algorithm to solve it.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.357-360
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• 2002

This paper is proposed about an efficient pipelined architecture for 3D graphics accelerator to reduce Cache miss ratio. Because cache miss takes a considerable time, about 20∼30 cycle, we reduce cache miss ratio to use pre-fetch. As a result of simulation, we figure out that the miss ratio of cache depends on the size of tile, cache memory and auxiliary cache memory. We can save 6.6% cache miss ratio maximumly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.10-21
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• 1997

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.263-264
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• 2006

On this study the performance of engineering workstation running OpenGL based application The following instructions are enhanced by configuring of the microprocessor and main memories. Single processors and more main memories are better than dual and less or same is confirmed.