• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.87-100
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• 2005

In this paper, we propose a new selective temporal error concealment algerian best suited for H.264/AVC. The proposed algorithm performs selective temporal error concealment depending on whether the lost block is at background or foreground. It the corrupted macroblock is decided as at background, then the simple temporal replacement is performed. Also we propose replacing a lost block at foreground with the selective average of respectively estimated blocks from the multiple reference frames. This paper supposes error-corrupted H.264/AVC video bitstreams over CDMA2000 (or UMTS) air interface. It is shown that under Flexible Macroblock Ordering (FMO) coding of H.264/AVC, the proposed algorithm provides PSNR gain up to 1.18dB compared to built-in algorithm in the K264/AVC test model. In addition, the proposed error concealment method has average PSNR improvement of 0.33dB compared with that under N-slice coding mode. The proposed algorithm also provides better subjective video quality than other conventional error concealment algorithms.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.2
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• Computers and Concrete
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• v.3 no.2_3
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• pp.79-90
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• 2006

This paper describes the results of an investigation into high mass-low velocity impact behaviour of reinforced concrete beams. Tests have been conducted on fifteen 2.7 m or 1.5 m span beams under drop-weight loads. A high-speed video camera has been used at rates of up to 4,500 frames per second in order to record the crack formation, propagation, particle spallation and scabbing. In some tests the strain in the reinforcement has been recorded using "Durham" strain gauged bars, a technique developed by Scott and Marchand (2000) in which the strain gauges are embedded in the bars, so that the strains in the reinforcement can be recorded without affecting the bond between the concrete and the reinforcement. The impact force acting on the beams has been measured using a load cell placed within the impactor. A high-speed data logging system has been used to record the impact load, strains, accelerations, etc., so that time histories can be obtained. This research has led to the development of computational techniques based on combined continuum/discontinuum methods (finite/discrete element methods) to permit the simulation of impact loaded reinforced concrete beams. The implementation has been within the software package ELFEN (2004). Beams, similar to those tested, have been analysed using ELFEN a good agreement has been obtained for both the load-time histories and the crack patterns.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.2
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• pp.892-911
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• 2019

Biometric recognition systems have been widely used for information security. Among the most popular biometric traits, there are fingerprint and face due to their high recognition accuracies. However, the security system that uses face recognition as the login method are vulnerable to face-spoofing attacks, from using printed photo or video of the valid user. In this study, we propose a fast and robust method to detect face-spoofing attacks based on the analysis of spatial frequency differences between the real and fake videos. We found that the effect of a spoofing attack stands out more prominently in certain regions of the 2D Fourier spectra and, therefore, it is adequate to use the information about those regions to classify the input video or image as real or fake. We adopt a divide-conquer-aggregate approach, where we first divide the frequency domain image into local blocks, classify each local block independently, and then aggregate all the classification results by the weighted-sum approach. The effectiveness of the methodology is demonstrated using two different publicly available databases, namely: 1) Replay Attack Database and 2) CASIA-Face Anti-Spoofing Database. Experimental results show that the proposed method provides state-of-the-art performance by processing fewer frames of each video.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• The Korean Journal of Nuclear Medicine
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• v.38 no.3
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• pp.259-267
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• 2004

Purpose: NEMA NU2-2001 was proposed as a new standard for performance evaluation of whole body PET scanners. in this study, system performance of Siemens CTI ECAT EXACT 47 PET scanner including spatial resolution, sensitivity, scatter fraction, and count rate performance in 2D and 3D mode was evaluated using this new standard method. Methods: ECAT EXACT 47 is a BGO crystal based PET scanner and covers an axial field of view (FOV) of 16.2 cm. Retractable septa allow 2D and 3D data acquisition. All the PET data were acquired according to the NEMA NU2-2001 protocols (coincidence window: 12 ns, energy window: $250{\sim}650$ keV). For the spatial resolution measurement, F-18 point source was placed at the center of the axial FOV((a) x=0, and y=1, (b)x=0, and y=10, (c)x=70, and y=0cm) and a position one fourth of the axial FOV from the center ((a) x=0, and y=1, (b)x=0, and y=10, (c)x=10, and y=0cm). In this case, x and y are transaxial horizontal and vertical, and z is the scanner's axial direction. Images were reconstructed using FBP with ramp filter without any post processing. To measure the system sensitivity, NEMA sensitivity phantom filled with F-18 solution and surrounded by $1{\sim}5$ aluminum sleeves were scanned at the center of transaxial FOV and 10 cm offset from the center. Attenuation free values of sensitivity wire estimated by extrapolating data to the zero wall thickness. NEMA scatter phantom with length of 70 cm was filled with F-18 or C-11solution (2D: 2,900 MBq, 3D: 407 MBq), and coincidence count rates wire measured for 7 half-lives to obtain noise equivalent count rate (MECR) and scatter fraction. We confirmed that dead time loss of the last flame were below 1%. Scatter fraction was estimated by averaging the true to background (staffer+random) ratios of last 3 frames in which the fractions of random rate art negligibly small. Results: Axial and transverse resolutions at 1cm offset from the center were 0.62 and 0.66 cm (FBP in 2D and 3D), and 0.67 and 0.69 cm (FBP in 2D and 3D). Axial, transverse radial, and transverse tangential resolutions at 10cm offset from the center were 0.72 and 0.68 cm (FBP in 2D and 3D), 0.63 and 0.66 cm (FBP in 2D and 3D), and 0.72 and 0.66 cm (FBP in 2D and 3D). Sensitivity values were 708.6 (2D), 2931.3 (3D) counts/sec/MBq at the center and 728.7 (2D, 3398.2 (3D) counts/sec/MBq at 10 cm offset from the center. Scatter fractions were 0.19 (2D) and 0.49 (3D). Peak true count rate and NECR were 64.0 kcps at 40.1 kBq/mL and 49.6 kcps at 40.1 kBq/mL in 2D and 53.7 kcps at 4.76 kBq/mL and 26.4 kcps at 4.47 kBq/mL in 3D. Conclusion: Information about the performance of CTI ECAT EXACT 47 PET scanner reported in this study will be useful for the quantitative analysis of data and determination of optimal image acquisition protocols using this widely used scanner for clinical and research purposes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.9-18
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• 2005

This paper presents the method of calculating the quantization level of the intra-frame in MPEG-4 video encoder. The intra-frame is an essential part in that the quality of the whole GOP is affected by the quality of this frame since the intra-frame, which works as a reference frame within GOP, continuously propagates through other frames. This work proposes how to use bits assigned for gaining the quantization level of the intra-frame, complexity of input images, and GOP structures. The result shows that while existing approaches have the decline in efficiency by using fixed values or show different qualifies depending on the characteristics of the images, the current approach shows the steady results in various images. Comparing with Q2 algorithm obtained in MPEG-4 VM, the approach suggested in this paper gains the benefit of maximum 3.49dB with some variations depending on the characteristics of the images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.406-414
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• 2005

The necessity for a technique to protect intellectual property of a digital content has been increasing, especially for the image/video contents which are the most favorite because of their high information-intensive property. According to this demand, this paper proposed a digital watermarking algorithm, which is recognized as the most promising technique. This algorithm targets MPEG compression system and the watermarking process is to be performed during the compression process. It inserts watermark only in Y components of I-frames. Experimental results showed that the proposed method satisfied both imperceptibility and robustness against various attacks. The PSNR difference between the compressed images(the average compression ratio was about 27:1 with Y:Cb:Cr=4:2:0 color format for TM5-based compression) with and without watermarking was only 1.8dB ($4.2\%$). In each case that the resulting image after an attack was reusable the normalized correlation between the extracted watermark and the original one was above 0.8.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.