Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Full-Search Block-Matching Motion Estimation Circuit with Hybrid Architecture for MPEG-4 Encoder

하이브리드 구조를 갖는 MPEG-4 인코더용 전역 탐색 블록 정합 움직임 추정 회로

  • Shim, Jae-Oh (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies) ;
  • Lee, Seon-Young (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies) ;
  • Cho, Kyeong-Soon (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
  • 심재오 (한국외국어대학교 전자정보공학부) ;
  • 이선영 (한국외국어대학교 전자정보공학부) ;
  • 조경순 (한국외국어대학교 전자정보공학부)
  • Published : 2009.02.25
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Abstract

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

본 논문은 시스톨릭 어레이와 덧셈기 트리를 조합한 하이브리드 구조를 갖는 MPEG-4 인코더용 전역 탐색 블록 정합 움직임 추정 회로를 제안한다. 제안된 회로는 적은 수의 클럭 싸이클로 움직임 추정을 할 수 있도록 시스톨릭 어레이를 활용하고, 필요한 회로 자원을 줄이기 위해서 덧셈기 트리를 활용한다. 1/2화소 움직임 추정을 위한 보간 회로는 6개의 덧셈기, 4개의 뺄셈기, 10개의 레지스터로 구성하였으며, 자원 공유 및 효율적인 스케줄링 기법을 통하여 성능을 향상시켰다. 정수화소 및 1/2 화소를 위한 움직임 추정 회로를 Verilog HDL을 사용하여 RTL에서 설계하였다. 130nm 표준 셀 라이브러리를 사용하여 합성한 논리 수준 회로는 218,257 게이트로 구성되었으며, D1($720{\times}480$) 이미지를 초당 94장 처리할 수 있다.

Keywords

References

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