• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Proceedings of the Korean System Dynamics Society
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• 2000.07a
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• pp.135-152
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• 2000

지배적 피드백 루프는 구조가 시스템의 행동을 유발한다는 점에 있어서 매우 중요한 개념이다. 본 논문에서는 지배적 피드백 루프의 전환을 완만한 전환(continuous shifts)과 급격한 전환(discrete shifts)의 두 가지로 분류하였다. 본 연구에서는 지배적 피드백 루프의 전환에 대한 인지적 편향을 세 가지의 가설로 분류하여 제시하였다. 이에는 1) 완만한 전환에 대한 인식의 실패, 2) 의사결정 자들의 급격한 전환에 의존하는 경향, 3) 지배적 피드백 루프의 인식에 있어서 수준변수와 변화율 변수간의 차이 등이 포함된다. 마지막으로 본 논문에서는 지배적 피드백 루프에 의한 인지적 편향이 의사결정과정의 시간지연과 정책 개입의 시기에 대하여 어떠한 시사점을 주는지에 관하여 논의하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.468-469
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• 2008

항공기, 차량, 고속의 비행체 등과 같은 동적인 플랫폼에서 표적을 추적하기 위한 영상 추적 시스템은 시선을 안정화하는 외부의 추적루프와 내부의 안정화 루프를 포함하는 구조로 되어 있다. 2축 김발을 사용하는 영상 추적 시스템의 추적루프는 크게 영상 추적기, 추적 제어기, 안정화 루프 등으로 구성되어 있다. 본 논문에서는 영상 추적 시스템의 추적 제어기를 설계하여 성능을 분석하고, 또한 설계된 제어기를 적용하여 영상 추적기의 시간지연에 의한 추적 루프 특성을 분석하였다. 마지막으로 설계된 추적 제어기를 영상 추적 시스템 시뮬레이터에 적용하여 고기동 고속의 비행체 환경에서 추적 루프 성능을 분석하였다.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1996.10a
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• pp.84-90
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• 1996

일반적으로 차실 음향 공동과 차체 팬널이 연성이 되는 계에 대한 소음 연성해석을 위한 해석 모델은 팬널과 공동이 직접적으로 연성이 되는 것으로 모델링되었다. 그러나 루프와 같은 팬널이 차실과 연성이 되는 경우, 루프의 진동은 차실에 직접적으로 전달되지 않고 루프 하단에 존재하는 갭과 내장판을 통하여 차실 소음에 영향을 미친다. 루프와 내장재 사이에 있는 갭의 매질은 주로 공기 도는 흡음재이다. 본 논문에서는 이러한 음향 구조 연성계를 이론적으로 해석 가능한 1차원 모델로 근사화하여 갭의 간격, 갭의 매질 특성, 내장재의 물성치 등의 변화에 따른 공동 내의 음향 응답 특성을 알아보고자 한다. 또한 위 결과를 에어갭을 고려한 3차원 차실 모델에 적용하고, 1/2 차실 모델에 대한 실험을 통하여 에어갭과 내장재의 효과를 검증한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.591-601
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• 2007

In this paper, the miniaturized radio frequency identification(RFID) tag antennas used in UHF band$(908.5{\sim}914MHz)$ are designed and fabricated by using the circular loop antenna(CLA). Miniaturization of CLA was possible to transform the structure of circular loop into the structure of meander line. In the case of double meander line CLA is reduced up to 83% compared with the general type CLA. The $S_{11}$, -10 dB bandwidth, and gain of double meander line CLA were -11.9 dB, 12 MHz(1.3%), and -1.18 dBd. Also, a small half-wavelength CLA using double meander line is designed and fabricated for flat snack bag coated aluminum. The antenna is reduced up to 92.1% except ground. It shows the $S_{11}$ of -16.5 dB, -10 dB bandwidth of 48 MHz(5%) and gain of -0.58 dBd. The radiation pattern shows omni-directional pattern in z-y plane(x-axis pol.). Through this result, we can confirm that miniaturized type CLAs using meander lines are suitable for miniaturized RFIB tag antennas with the UHF band.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.91-99
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• 2001

Since roost of the program execution time is spent in the loop structure, the problem of extracting parallelism from sequential loop has been one of the most important research issues. However. roost programs have Implicit interprocedure parallelism. This paper presents a generalized method extracting parallelism in loops having the procedure calls. Most parallelization of loops having procedure calls focus on the uniform code where data dependency distance is constant. We present algorithms which can be applied to uniform code, nonuniform code, and complex code. The performance of the proposed algorithm, loop extraction, loop embedding and procedure cloning transformation methods have been evaluated using CRAY-T3E. The result shows the effective of the proposed algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5447-5451
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• 2012

This paper presents a pattern-switchable microstrip patch antenna with loop structure. The loop structure for switchable radiation beam pattern is connected with feeding line of the microstrip patch antenna. As changing switch on/off state, the radiation beam pattern can be changed. The target frequency is 2.4 GHz and maximum radiation gain is 3.2dBi. The proposed antenna is useful for diversity antenna and smart antenna in modern wireless communication including MIMO (Multi-Input Multi-Output) and WLAN system. The sizes of the rectangular patch and the ground plane are $28mm{\times}28mm$ and $40mm{\times}50mm$, respectively. The simulation and experimental results show that the antenna radiation pattern can be changed with switch on/off configuration.