• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1418-1419
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• 2011

차세대 전력 반도체인 고전압 GaN 쇼트키 장벽 다이오드의 역방향 특성을 개선하기 위해서 열 산화공정이 제안되었다. AlGaN/GaN 에피탁시 위에 쇼트키 장벽 다이오드 구조가 제작되었으며, 쇼트키 컨택은 증착 후 $450^{\circ}C$에서 산화되었다. 열 산화공정이 메사 측벽의 AlGaN 및 GaN 표면에 $AlO_x$ 및 $GaO_x$를 형성하여 표면으로 흐르는 누설전류를 억제한다. 표면 및 GaN 버퍼를 통한 누설전류는 열 산화 공정 이후 100 ${\mu}m$-너비당 51.3 nA에서 24.9 pA로 1/2000 배 수준으로 감소하였다. 표면 산화물 형성으로 인하여 생성된 Ga-vacancy와 Al-vacancy는 acceptor로 동작하여 surface band bending을 증가시켜 쇼트키 장벽 높이를 증가시킨다. 애노드-캐소드 간격이 5 ${\mu}m$인 제작된 소자는 0.99 eV의 높은 쇼트키 장벽 높이를 획득하여, -100 V에서 0.002 A/$cm^2$의 낮은 누설전류를 확보하였다. 애노드-캐소드 간격이 5에서 10, 20, 50 ${\mu}m$로 증가되면 소자의 항복전압은 348 V에서 396, 606, 941 V로 증가되었다. 열 산화공정은 전력용 GaN 전자소자의 누설전류감소와 항복전압 증가를 위한 후처리 공정으로 적합하다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.10-14
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• 2009

We propose a trapezoidal gate AlGaN/GaN high electron mobility transistor(HEMT) to improve the breakdown voltage characteristics and its feasibility is investigated by two-dimensional device simulations. The use of a trapezoidal gate structure appears to be quite effective in dispersing the electric fields concentrated near the gate edge on the drain side from the simulation result. We find that a peak value of the electric field along the 2-DEG channel is reduced by 30%, from 4.8 to 3.5 MV/cm and thereby, the breakdown voltage(Vbr) of the proposed AlGaN/GaN HEMT is increased by about 40%, from 49 to 69 V, compared to those of the standard AlGaN/GaN HEMT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of IKEEE
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• v.26 no.4
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• pp.728-735
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• 2022

In this work, we investigated a high-voltage (~4.5 kV) 4H-SiC power DMOSFET with modifications of current spreading layer (CSL), which was introduced below the p-well region for low on-resistance. These include the following: 1) a thickness of CSL (T_CSL) from 0 um to 0.9 um; 2) a doping concentration of CSL (N_CSL) from 1×10¹⁶ cm^-3 to 5×10¹⁶ cm^-3. The design is optimized using TCAD 2D-simulation, and we found that CSL helps to reduce specific on-resistance but also breakdown voltage. The resulting structures exhibit a specific on-resistance (R_on,sp) of 59.61 mΩ·cm², a breakdown voltage (V_B) of 5 kV, and a Baliga's Figure of Merit (BFOM) of 0.43 GW/cm².

• Journal of the Korean Magnetics Society
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• v.12 no.5
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• pp.168-173
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• 2002

Electrostatic discharge characteristics were studied by connecting human body model (HBM) with tunneling magnetoresistance (TMR) device in this research. TMR samples were converted into electrical equivalent circuit with HBM and it was simulated utilizing PSPICE. Discharge characteristics were observed by changing the component values of the junction model in this equivalent circuit. The results show that resistance and capacitance of the TMR junction were determinative components that dominate the sensitivity of the electrostatic discharge(ESD). Reducing the resistance oi the junction area and lead line is more profitable to increase the recording density rather than increasing the capacitance to improve the endurance for ESD events. Endurance at DC state was performed by checking breakdown and failure voltages for applied DC voltage. HBM voltage that a TMR device could endure was estimated when the DC failure voltage was regarded as the HBM failure voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.95-100
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• 1990

We fabricated primary and secondary seed grains. Primary seed grains having larger grain size were obtained under the conditions that were 2.0mol.% $BaCO_3$ and 10 hours sintering. The amount of primary seed grain that yield the largest secondary seed grain was chosen as 3wt.% and we fabricated the low voltage varistors which were jointed the low voltage-oriented ZnO varistor system made by conventional method with the secondary seed grains. As a result, the ZnO varistors under those conditions showed approximately 10V/mm of nonlinear resistance and 15-22 of nonlinear exponent.

• The Korean Journal of Rheology
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• v.10 no.3
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• pp.165-172
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• 1998

본논문에서는 전기장 부하에 따라 유동성질이 변화하는 ER유체의 빙햄특성을 실험 적으로 연구하였다. 특히 ER유체의 빙행특성에 영향을 주는 여러인자중 전극 간격 및 재질 에 따른 ER유체의 항복전단응력과 전류밀도의 변화를 온도에 따라 고찰하였다. 이를 위하 여 전극 간격을 가변시킬수 있는 전기 점도계를 세가지 재질로 자체 제작하였다. 전극간격 은 0.75 mm, 1.00mm 및 1.25 mm 로 설정하였으며 전극 재질은 스테인레스 스텔, 동 그리 고 기계구조용 탄소강(SMS45C)을 사용했다. 한편 실험에 사용된 ER유체는 자체 조성한 수 계 ER유체인 ERF-1과 외국의 우수하다고 알려진 비수계 ER유체인 ERF-2 두가지를 선택 하였다. 실험은 $25^{\circ}C$와 7$0^{\circ}C$ 및 10$0^{\circ}C$에서 수행하였으며 전기장은 0-4kV/mm 범위에서 온 도 및 ER유체의 종류에 따라 부하 가능한 전압까지 공급하였다. 전단변형률 50, 100, 150, 200, 400, 600, 800, 1000 및 1200 s-1에서 얻은 전단응력 실험결과로부터 최소오차선형법을 이용하여 전단변형률 영에서 동적 항복전단응력 값을 도출하였으며 그결과로부터 전극 간격 및 재질에 따른 ER효과의 변화를 고찰하였다. 또한 상온과 10$0^{\circ}C$에서 4kV/mm의 전기장을 부하하여 전기장에대한 ER유체의 응답특성을 실험을 수행했다.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.65-66
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• 2006

AIGaN/GaN 고전자 이동도 트랜지스터 (High Electron Mobility Transistors, HEMTs)는 와이드 밴드-갭과 높은 항복 전계 및 우수한 채널 특성으로 인해 마이크로파 응용분야와 전력용 반도체에서 각광받고 있다. 최근, 전력 응용분야에서 요구되는 높은 항복 전압과 출력, 우수한 주파수 특성을 획득하기 인해 이중 게이트 AIGaN/GaN HEHTs에 관한 연구가 발표되고 있다. 본 논문에서는 AIGaN/GaN HEMTs에 이중 게이트를 적용하여, 두 개의 게이트와 드레인, 소스의 누설 전류를 각각 측정하여 이중 게이트 AIGaN/GaN HEMTS의 누설 전류 메커니즘을 분석하였다. 또한 제안된 소자의 $SiO_2$ 패시베이션 전 후의 누설 전류 특성을 비교하였다. $SiO_2 $ 패시베이션되지 않은 소자의 누설 전류는 드레인, 소스와 추가 게이트로부터 주 게이트로 흐른 반면, 패시베이션 된 소자 누설 전류는 드레인으로부터 주 게이트 방향의 누설 전류만 존재하였다. $SiO_2$ 패시베이션 된 소자의 누설 전류는 (87.31 nA ) 패시베이션 되지 않은 소자의 누설 전류 ( $8.54{\mu}A$ )에 비해 의게 감소하였다.