• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.1-6
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• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.1-6
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• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.1-6
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• 2021

The paper proposes the design of AES-based encryption chip for IoT security. ROM based S-Box implementation occurs a number of memory space and some delay problems for its access. In this approach, S-Box is designed by pipeline structure on composite field GF((22)2) to get faster calculation results. In addition, in order to achieve both higher throughput and less delay, shared S-Box are used in each round transformation and the key scheduling process. The proposed AES crypto-processor is described in Veilog-HDL, and Xilinx ISE 14.7 tool is used for logic synthesis by using Xilinx XC6VLX75T FPGA. In order to perform the verification of the crypto-processor, the timing simulator(ModelSim 10.3) is also used.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.1-6
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• 2021

In this paper, an efficient implementation of AES encryption algorithm is presented for CCTV image security using C# language. In this approach, an efficient S-Box is first designed for reducing the computation time which is required in each round process of AES algorithm, and then an CCTV image security system is implemented on the basis of this algorithm on a composite field GF(((22)2)2). In addition, the shared S-Box structure is designed for realizing the minimized memory space, which is used in each round transformation and key scheduling processes. Through performance evaluation, it was confirmed that the proposed method is more efficient than the existing method. The proposed CCTV system in C# language using Visual studio 2010.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• KSBB Journal
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• v.10 no.5
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• pp.499-509
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• 1995

PU.1, a tissue-specific transcription activator, binds to a purine-rich sequence(5'-GAGGAA-3') called PU box. The PU.1 cDNA consists of an open reading frame of 816 nucleotides coding for 272 amino acids. The amino terminal end is highly acidic, while the carboxyl terminal end is highly basic. Transcriptional activation domain is located at the amino terminal end, while DNA binding domain is located at the carboxyl terminal end. Activation of PU.1 transcription factor is supposed to be accomplished by the phosphorylation of serine residue(s). There exist 22 serines in the PU.1. Five(the 41, 45, 132$.$133, and 148th) of the serines(plausible phosphorylation site by casein kinase II), are the primary targets of interest in elucidating the molecular mechanism(s) of the action of the PU.1 gene. In this study, PU.1 cDNA coding for the five serine residues(41th AGC, 45th AGC, 132$.$133th AGC$.$TCA, and 148th TCT), was mutated to alanine codon(41th GCC, 45th GCC, 132$.$133th GCC$.$GCA, and 1481h GCT), respectively, by Splicing-Overlapping-Extension(SOE) using Polymerase Chain Reaction(PCR). And each mutated cDNA fragments was ligated into pBluescript KS＋ digested with HindIII and Xba I, to generate mutant clones named pKKS41A, pRKS45A, pMKS132$.$133A, and pMKS148A. The clones will be informative to study the "Structure and Function" of the immu-nologically important gene, PU.1.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.5A
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• pp.407-415
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• 2010

In Korea, more than 90% of the total number of steel bridges built for 40~70 m span length is a steel box-girder bridge type. A steel box-girder bridge is suitable for long span or curved bridges with outstanding flexural and torsional rigidity as well as good constructability and safety. However, a steel box-girder bridge is uneconomical, requiring many secondary members and workmanship such as stiffeners and ribs requiring welding attachments to flanges or webs. Therefore, in US and Japan, a plate girder bridge, which is relatively cheap and easy to construct is generally used. One type of the plate girder bridge is the two- or three-main girder plate bridge, which is a composite plate girder bridge that minimizes the number of required main girders by increasing the distance between the adjacent girders. Also, for the simplification of girder section, the stiffener which requires attachment to the web is not required. The two-main steel girder plate bridge is a representative type of plate girder bridges, which is suitable for bridges with 10 m effective width and has been developed in the early 1960s in France. To ensure greater safety of two- or three-main girder plate bridges, a larger steel section is used in the bridge domestically than in Europe or Japan. Also, the total number of two- or three-main girder plate bridge constructed in Korea is significantly less than the steel box girder bridge due to a lack of designers' familiarity with more complex design detailing of the bridge compare to that of a steel box girder bridge design. In this study, a new construction method called Turn Over method is proposed to minimize the steel section size used in a two- or three-main girder plate bridge by applying prestressing force to the member using confining concrete section's weight to reduce construction cost. Also, a full scale 20 m Turn Over girder specimen and a Turn Over girder bridge specimen were tested to evaluate constructability and structural safety of the members constructed using Turn Over process.

• Journal of the Korean Chemical Society
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• v.59 no.5
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• pp.397-406
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• 2015

ZnO, II-VI group inorganic compound semi-conductor, has been receiving much attention due to its wide applications in various fields. Since the ZnO has 3.37 eV of a wide band gap and 60 meV of big excitation binding energy, it is well-known material for various uses such the optical property, a semi-conductor, magnetism, antibiosis, photocatalyst, etc. When applied in the field of photocatalyst, many research studies have been actively conducted regarding magnetic materials and the core-shell structure to take on the need of recycling used materials. In this paper, magnetic core-shell ZnFe₂O₄@SiO₂ nanoparticles (NPs) have been successfully synthesized through three steps. In order to analyze the structural characteristics of the synthesized substances, X-ray diffraction (XRD), scanning electron microscopy (SEM), and Fourier transform infrared spectroscopy (FT-IR) were used. The spinel structure of ZnFe₂O₄ and the wurtzite structure of ZnO were confirmed by XRD, and ZnO production rate was confirmed through the analysis of different concentrations of the precursors. The surface change of the synthesized materials was confirmed by SEM. The formation of SiO₂ layer and the synthesis of ZnFe₂O₄@ZnO@SiO₂ NPs were finally verified through the bond of Fe-O, Zn-O and Si-O-Si by FT-IR. The magnetic property of the synthesized materials was analyzed through the vibrating sample magnetometer (VSM). The increase and decrease in the magnetism were respectively confirmed by the results of the formed ZnO and SiO₂ layer. The photocatalysis effect of the synthesized ZnFe₂O₄ @ZnO@SiO₂ NPs was experimented in a black box (dark room) using methylene blue (MB) under UV irradiation.