• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.11
• /
• pp.109-118
• /
• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.4
• /
• pp.219-225
• /
• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

• Journal of IKEEE
• /
• v.5 no.1 s.8
• /
• pp.43-51
• /
• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 2017.05a
• /
• pp.180-187
• /
• 2017

Major design targets such as test cell type, cell flow, cell bypass ratio, approach velocity, cell depression, front cell distortion, noise level and vibration level to construct a new 150,000 lbf thrust aircraft engine test facility were established. Based on the final aerodynamic and acoustic performance tests conducted at the newly constructed test facility, it was found that the new test facility is judged to be excellent and meets design targets.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.254-256
• /
• 2019

본 논문은 파워셀 구조를 기반으로 설계된 양극성 펄스 전원장치에 대하여 소개한다. 파워셀은 풀브릿지 구조를 기반으로 설계되었으며, 833V를 출력하는 각 셀이 직렬로 연결되어 고전압을 생성하는 구조를 갖는다. 모든 파워셀의 방전 스위치를 구동하기 위해서 절연된 전력과 신호의 동시공급이 가능한 게이트 회로 구동방안이 제안되었다. 양극성 펄스 출력을 위한 파워셀의 각 래그의 단락을 방지하기 위한 게이트 회로가 설계되었다. 설계된 양극성 펄스 파워 모듈레이터의 동작을 검증하기 위해 테스트 회로가 구현되었다. 시험회로는 출력전압, 펄스 폭, 반복률 가변 조건에서 테스트 되었으며, 이를 통해 제안하는 양극성 펄스 파워 모듈레이터의 구조 및 게이트 구동회로의 신뢰성이 검증되었다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.2
• /
• pp.84-92
• /
• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.6
• /
• pp.70-76
• /
• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.26-31
• /
• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of KIISE:Information Networking
• /
• v.37 no.1
• /
• pp.16-26
• /
• 2010

We present a testbed for collecting log information and evaluating network security under various attacks. This testbed is modeled on real Internet, where attack traffic coexists with normal traffic. Attacks can be produced either by attack tools directly or by data sets including attack traffic. It costs less time and money than existing ones which are both costly and often time consuming in constructing. Also, it can be easily revised or extended according to the traffic types or the uses. Therefore, using our testbed can make various tests more efficient and facilitate collecting log information of sensors with attacks. We discuss how to use our testbed through replay procedures of DDoS attack and worm. We also discuss how we surmount some difficulty in constructing the testbed.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.296-297
• /
• 2017

태양광 발전에 있어서 실제 태양광 셀 특성은 날씨와 같은 환경 요인에 의존적이기 때문에 다양한 동작 조건에 대한 태양광 셀의 특성을 전력변환장치를 통해 테스트하기 위해 많은 시간과 비용이 소요된다. 이러한 문제를 해결하기 위해 Power Hardware-In-the-Loop Simulation (PHILS) 기술을 이용해 태양광 발전용 전력변환장치 시제품의 테스트 시간 및 비용을 단축할 수 있다. PHILS는 실시간 모의시험장치와 외부 입력이 가능한 전력변환장치로 구성되며, 해당 장치에서 모델의 동특성을 실시간으로 연산하기 때문에 모델이 복잡할수록 고성능 모의시험장치가 요구된다. 태양광 셀 모델의 출력 전압은 수치해석 기법을 통해 계산되고, 수치해석 기법의 종류와 초기 값에 따라 연산 시간 등의 성능이 변화하므로 적절한 기법을 선정하여 모델의 연산시간을 감소시킬 수 있다. 본 논문에서는 수치 해법 분석을 통한 태양광 발전의 PHILS를 위한 태양광 셀 모델의 연산 성능향상 기법을 제시하고, 실제 태양광 발전용 PHILS를 구현하여 실험적으로 제안하는 기법의 성능을 검증한다.