• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.848-855
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• 2004

In this paper, we propose a new channel identification technique for long code DS/CDMA DMB down link system which estimate the channel response based on the signal space vector only, unlike the most conventional subspace method relying on the orthogonal property of noise space vectors to the signal space vector. Because of this property of the proposed method, it is optimum and practical in manipulation of the covariance matrix to be analyzed. In the paper, we derive the mathematical expression necessary to clarify the proposed method and show the relevant simulation and numerical results to verify the validity of the proposed algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.581-584
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• 2002

The graylevel image scanning system realization and design using CIS(Contact Image Scanning)be amenable to recognize a papers, OMR and OCR sheet is proposed. The design technique is used CIS scanning sensor in fixing step motor and is optimized with DSP processor for image processing., and transfer input image data par line in feeding a step unit to PC on the USB interfacer. This system is portable and A4 size scanning and keeps image scan processing speed 300mm/sec The recognition percentage has 98% on the OCR and bar codes.

• Annual Conference of KIPS
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• 2024.05a
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• pp.851-853
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• 2024

본 논문에서는 MediaPipe 라이브러리 및 OpenCV 를 활용한 포즈 추정 및 체형 인식 알고리즘을 통해 사용자의 체형과 선호도에 맞는 의류를 가상으로 입어볼 수 있는 생성형 FashionNet 을 제안한다. 구체적으로는 먼저 웹 카메라를 통해 얻어진 사용자의 외형 이미지로부터, 사용자의 신체 포즈를 추정하고, OpenCV 코드를 통해 사용자의 신체 윤곽을 검출한다. 이후 가상 옷장 데이터베이스로부터 선택된 가상 의류를 사용자의 신체 윤곽에 맞춰 입혀진 가상 피팅 이미지를 생성한다. 특히, 본 논문의 FashionNet 은 사용자와 카메라 간의 거리에 따른 인체 비율을 사전 실험으로 미리 설정해놓음으로써, 카메라와 사용자간의 거리에 관계없이 의류 사이즈가 사용자의 신체 조건에 맞게 자동으로 피팅되는 특징을 갖는다. 또한 가상 옷장 데이터베이스로부터 의류 아이템 선정의 편의를 제공하기 위해, 가상 현실 속에서 스크린상의 메뉴 버튼과 사용자의 포즈 동작간의 상호작용을 통해 FashionNet 의 다양한 기능을 수행할 수 있는 증강현실(AR) 기법을 적용하였다. 가상 옷장 데이터베이스를 사용한 다양한 가상 피팅 체험 실험을 통해 온라인상에서 자기가 원하는 의류를 가상으로 착용해 볼 수 있고 이를 통해 구매를 결정하는 등의 FashionNet 의 유효성과 가능성을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.427-435
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• 2009

Users are able to search and read interesting items and hence click hyperlink linked to the item which is detailed content unit such as menu, login, news, video, etc. Small screen like mobile device is very difficult to viewing all web contents at once. Browsing and searching for interesting items by scrolling to left and right or up and down is discomfort to users in small screen. Searching and displaying directly the item preferred by users can reduces difficulty of interface manipulation of mobile device. To archive it, web contents based on desktop will be segmented on a per-item basis which component unit of web contents. Most segment algorithms are based on segment method through analysis of HTML code or mobile size. However, it is difficult to extract item blocks. Because present web content is getting more complicated and diversified in structure and content like web portal services. A web content segment algorithm suggested in this paper is based on extracting item blocks is component units of web contents.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of Digital Convergence
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• v.8 no.1
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• pp.93-107
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• 2010

Performance of software development is measured by two major criteria - roductivity and quality. Although the criteria is empirically tested in software engineering research, they often present with a limited way under consideration of a few factors or contexts for developers to focus on the either productivity facets or quality facets. Analyzing data on software development performance collected over a 13-year period from 20 countries, we investigated how major software development factors - development type, development platform, development technique, language type, DBMS, methodology, methodology acquisition, CASE,, summary of work effort, resource level, max team size, affect the performance of software development. The results suggest that productivity and quality of software development are affected by different factors and context: function points, line of code, extreme defects, major defects, or minor defects. This research provides the empirical evidence that the two performance criteria require for software developer to have careful attention to find the optimal balance between the two performance criteria.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.220-223
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• 2016

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.95-105
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• 2010

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Since it aims to provide low cost and low power communication for ubiquitous communication, it requires high level of optimization in implementation. Recently, there have been many studies on the performance evaluation of IEEE 802.15.4 MAC protocol. According to the results of the studies, it is tendency that the transceiver is implemented to SoC type. On the implementation, the specific functions of MAC like CSMA-CA and MAC frame handling is designed to hardwired functions. In this paper, we implemented the protocol with hardwired low MAC (HL-MAC) and its state machine for the optimization from the physical layer and MAC layer. it has the characteristics of the small code size and the enhanced power consumption.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.