• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2247-2248
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• 2008

비접촉 터치식 조명 스위치의 감도에 관한 실험을 하였다. 유리, 목재(파티클 보드), 플라스틱의 세 종류 재질에 대해 다양한 두께의 판을 이용하여 스위치 전극을 고정한 후, 스위치가 안정적으로 동작하는 커패시턴스를 실험적으로 찾아보았다.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.2
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• pp.29-34
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• 1995

본 논문에서는 콤팩트 형광램프용 Dimming형 전자식 안정기의 설계에 있어서, 인버터 공진탱크의 커패시턴스값을 변화시킬 때 전압이득곡선을 분석하여 최적의 회로정수를 결정하는 방법을 제안하였다. 또한 하프브리지 인버터회로의 회로정수에 대한 PSpice 시뮬레이션을 행하여 램프전압과 전류값을 구하였고, 실제 전자식 안정기를 제가하고 시동특성과 조광특성을 비교분석하였다. 시동특성은 일반 전자식 안정기와 거의 동일하였으며, 조광특성은 전체 광출력의 5%까지 안정동작되어, 제안된 방법이 뛰어남을 확인하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.71-72
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• 2015

배터리의 랜들 등가회로 모델은 기본적으로, 전달 저항 Rct, 전기 이중층 커패시턴스 Cdl, 내부저항 Ri, 그리고 개방회로전압 Voc의 4가지 파라미터로 구성 된다. 본 논문은 실험에 의해 리튬이온 배터리의 모델링을 위한 기본적 4가지 파라미터를 추출하고 운전조건에 따른 특성을 분석한다. 분석 결과를 이용하여 본 연구자에 의하여 제작된 전기 스쿠터의 SOC(State of Charge)를 추정하는 알고리즘을 제안한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.177-186
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• 2012

In this paper, we propose a design method that the crosstalk of probe connector pins satisfy the limitation of -30 dB. The parameters(inductance and capacitance) were extracted in the grid-structured probe connector pin system, and it is shown that the new parameters are easily calculated with increasing ground pin numbers using the previously calculated parameters. In addition, the crosstalk reduction algorithm by employing more grounds around the signal pin has been suggested, and it is confirmed that the suggested method is quite effective especially for the reduction of inductive couplings. Finally, we suggested the correlation between the pitch and the length of the pins to satisfy the crosstalk limitation of -30 dB with the given number of ground pins, which will be quite useful when design a probe connector pin system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.18-21
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• 2009

In the digital system, ROM has a large power-consumption and a speed-bottleneck. According to gradual growth of system speed, ROM is demanded to have low-power consumption and high-speed operation design. The ROM adapted in FFT or FIR filter needs method of sequential accessed addressing. We proposed a reduction method for the number of storage cells in this paper. The number of storage cells which is connected with bi-line is reduced by the proposed method so that the capacitance value of bit-time is reduced. In this case, delay time, and power consumption are reduced. Design result of ROM in this paper using the proposed method could reduce up to 86.3% of storage cell '1' compare with conventional method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.59-64
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• 2013

In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.68-79
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• 2006

Electrical capacitance tomography (ECT) is a non-invasive imaging reconstruction technique that aims at visualization of cross sectional permittivity distribution of dielectric object based on the measured capacitance. There are lots of iterative image reconstruction methods to accelerate convergence rate and enhance quality of reconstructed image, Among them iterative Landweber method is one of the widely used reconstruction algorithm in En. In this paper, modified generalized Landweber method is proposed to accelerate convergence rate. In doing so, acceleration term is considered to the generalized Landweber method with shaping matrix and an optimal step length is determined analytically. Extensive computer simulations are provided to illustrate the reconstruction performance of the proposed algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.2
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• pp.141-146
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• 2009

A triangular microstrip antenna with T-shaped slits is proposed for tunable dual-band applications. The proposed antenna is designed using chip capacitors as a prototype. From this result the capacitor can be replaced to a varactor diode to control capacitance value. Since the input impedance of the antenna can be varied with the value of the chip capacitors on the T-shaped slits, the resonant frequency may be changed. The return losses are better than 10 dB at the lower band of $0.78{\sim}1.21$ GHz and 20 dB at the upper band of $1.97{\sim}2.17$ GHz, respectively. This antenna has the bandwidth of about 10 MHz and 50 MHz at each band. The peak gains of the antenna yield 0 dBi at the lower band and 3 dBi at the upper band, respectively. Details of the antenna design are described, and its performances are presented and analyzed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1789-1796
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• 2012

In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.