• Journal of the Korean Magnetics Society
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• v.18 no.2
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• pp.58-62
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• 2008

$Ni_{0.4}Zn_{0.4}Cu_{0.2}Fe_2O_4$ ferrite was fabricated by solid stat reaction method and sol-gel method. Because of the drawbacks of each method, we combined these two methods together. We proposed and experimentally verified that nanocrystalline ferrite additive was effective on improving the densification behavior and magnetic properties of NiZnCu ferrites for multilayer chip inductors. The initial permeability of the toroidal core Sample with 20 wt% nanocrystalline ferrite increased from 78.1 to 178.2 as annealing temperature is increased from $880^{\circ}C$ to $920^{\circ}C$. The density, shrinkage and saturation magnetization were increased with increasing annealing temperature, which was attributed to the decrease of additive grain size and increase of sintering density.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1521-1523
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• 2002

본 논문에서는 1.58 ${\times}$ 0.82 ${\times}$ 0.94 $mm^3$크기의 H 형태의 솔레노이드형 RF 칩 인덕터를 코일의 직경과 권선수를 변화시키면서 제작하였고, 그들의 고주파 성능을 비교 분석하였다. 저손실 $Al_2O_3$재료를 코아로 $30{\mu}m{\sim}40{\mu}m$의 여러 직경을 가진 Cu를 코일로 사용하였다. 인덕터의 인덕턴스(L), 품질계수(Q), 저항(R), 임피던스(Z) 그리고 커패시턴스(C) 등의 주파수 특성은 HP4291B로 측정하였다. 실험결과 동일권선수에 대해 코일직경이 자을수록 L, Q, R, 그리고 Z등이 증가하였고, 그 증가폭은 권선수가 클수록 커지는 경향이 있음을 알 수 있었다. 그러나 코일직경이 작을수록 기생 커패시턴스 효과가 빨리 나타나 자기 공진주파수 효과가 감소하는 경향을 보이고 있음을 확인하였다. 코일직경이 $3{\mu}m$이고 권선수가 6인 경우에 대표적인 값들은 다음과 같다. L=31.4nH(at 250MHz), Q=49.6(at 700MHz), R=0.362${\Omega}$(at 1MHz)

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.96-104
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• 2007

In this paper, the field solver based deembedding technique for the on-chip inductors to deembed the pad and surrounding ground effect was described, and the results from field solver based deembedding techniques and measurement based matrix calculation method were compared. In addition, LNA circuit is designed by using deembedded inductors and fabricated by using standard $0.25{\mu}m$ CMOS process, in the range over the 2.5GHz it shows the good agreements between measurement and simulation results when the proper deembedding was adapted. Supposed deembedding techniques can be used to get the pure on-chip devices's values and adapted to design accurate RFIC circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.17-22
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• 2011

To propose effective signaling scheme for inductive coupling link, inductive coupling channel and signaling schemes are analyzed. For fair comparison of various signaling schemes, a signal quality factor ($Q_{signal}$) is introduced and the NRZ signal scheme shows better signal quality factor than BPM signaling schemes. For simulation, the transmitter for inductive coupling link is designed with 0.13 ${\mu}m$ CMOS process and the inductor is modeled as spiral inductor in chip.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.443-447
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• 2003

In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.227-227
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• 2003

캐패시터, 인덕터 등의 전자부품들은 적층기술 및 표면 실장 기술 등을 이용하여 적층형 칩형태로 제작되고 있다. 적층형 칩형태의 전자부품들은 전자기적 특성을 부여하는 세라믹스와 전극역할을 하는 금속으로 구성되어 있으며, 전극 부분은 크게 내부전극과 외부전극으로 구분된다. 고장이 발생하게 되면 고장의 형태를 의미하는 고장모드(failure mode)와 제품을 고장에 이르게하는 물리, 화학적, 기계적 과정을 의미하는 고장기구(failure mechanism)을 조사하게 된다. 전자부품에서 고장이 발생하였을 경우, 1차적인 분석대상은 전극재인데 전극재에 기인한 고장으로는 세라믹스와 전극재 사이의 열팽창계수 차이에 기인한 박리현상(Delamination), 인쇄불량에 의한 단락 및 두께 불량, 세라믹스와 전극재 사이의 반응, 산화에 의한 부식 등이 있다. 이러한 고장은 급격한 주위 환경의 변화에 의한 것보다는 일정수준의 스트레스가 축적되어 발생하며, 수명을 예측하기 위해서는 고장의 원인을 규명하고 그 원인에 의한 가속 시험을 수행하는 것이 일반적인 방법이다. 본 연구에서는 Ag 외부 전극재의 수명을 예측하고자 가속시험을 수행하였고, 고장 분석 통하여 Ag외부 전극재의 특성 및 문제점 등을 정확히 파악하기 위한 연구를 하였다.

• Information and Communications Magazine
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• v.28 no.11
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• pp.24-30
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• 2011

본고에서는 소형 고집적 이동단말기용 패키지를 위해 구현 되고 있는 능/수동소자 내장형 패키지 기술에 대해 알아보고자 한다. 능/수동소자내장형 패키지 기술은 IC 칩과 같은 능동 소자와 저항, 커패시터, 인덕터와 같은 수동소자 부품들을 패키지 기판 내부에 내장시켜 소형화를 추구함과 더불어 칩과 수동소자간의 접속 길이를 짧게 해서 전기적 성능을 향상시키실 수 있는 패키징 기술이다. 본 원고에서는 PCB기술에 기반을 둔 embedded active device 기술과 웨이퍼 레벨 패키징 기술에 기반을 둔 fan-out embedded wafer level package 기술 동향에 대해 서술하고 그 특정들을 비교 분석하였으며 이 기술들에 대환 동향을 살펴보고자 한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.539-546
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• 2007

In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Journal of the Korean Ceramic Society
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• v.40 no.1
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• pp.31-36
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• 2003

In this study, nano-sized NiCuZn-ferrites for the multi-layered chip inductor application were prepared by a coprecipitation method and its electromagnetic properties were analyzed. Also, the property of low temperature sintering were studied with the initial heat treatment of powder.$(Ni_{0.4-x}Cu_xZn_{0.60})_{1+w}(Fe_2O_4)_{1-w}$ (x=0.2, w=0.03) were calcined at $300^{circ}C~750^{circ}C.$ The sintered NiCuZn-ferrites at $900^{\circ}C$ showed good apparent density $4.90g/cm^3,$ and magnetic properties of initial permeability 164 and quality factor 72. As the calcination temperature increase, the grain size of NiCuZn-ferrite increased with irregular grain distribution and its magnetic properties were deteriorated.