• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1115-1122
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• 2003

In this paper we fabricated microchip antenna operating in bluetooth frequency bands(2.402∼2.480GHz). The antenna has a size of about 54mm${\times}419mm${\times}40.8mm, giving a total bluetooth PCB for support and chip of about 11mm${\times}44mm${\times}41.6mm. Bandwidth of the designed and fabricated chip antenna for bruetooth is 10.71 % at the resonated frequency of 2.45GHz and the resonant frequency and bandwidth versus change of any arbitrary feed point is observed. also, E-plane and H-plane in the Measured radiation pattern characteristic of chip antenna is compared and analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.273-279
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• 2001

This paper describes a design and implementation of ISDN system on a chip which provides ISDN service and used to develop a low-price multimedia communication terminal. This ISDN SOC is an ISDN system control chip which has 32bit RISC processor, and it includes ISDN S interface transceiver, G.711 voice CODEC, PC interface for data communication, ISDN protocol which includes Q.931 call control protocol and internet protocol. It provides good solution to develope ISDN terminal equipment and ISDN terminal adaptor which connected with basic rate interface, because it minimize external peripheral devices.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.4
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• pp.87-98
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• 2002

Software has been developed very fast as information has become important value. Illegal software copy has been the main problem of developing software business. Recently used protecting lock system for software copy has not guaranteed perfectly from easily cracked-defense system. This paper, therefore, proposes 96-bit block cipher with 112-bit length to replace a DES(Data Encryption Standard) algorithm. Security chip by ASIC(Application Specific Integrated Circuit) security module is presented for software copy protection. Then, an auto block protecting algorithm is designed for the security chip. Finally, controlling driver and library are built for the security chip.

• Ceramist
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• v.6 no.1
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• pp.13-20
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• 2003

• The Monthly Technology and Standards
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• s.27
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• pp.66-69
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• 2004

• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.5
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• pp.259-267
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• 2001

칩의 집적도에 비례하여 설계검증 및 칩 제작 후의 결함점검은 갈수록 어려워지며 이러한 테스트 문제의 원초적 해결을 위하여 다양한 테스트설계 기술이 널리 개발되고 있다. 상위 수준의 테스트설계에서는 회로의 기능에 대해서는 알 수 있으나 구조에 대해서는 알 수 없고, 하위 수준의 테스트설계에서는 회로의 구조를 알 수 있으나 기능은 알 수 없다. 따라서 테스트 설계는 기능을 기술하는 상위 수준에서부터 고려되어 하위 게이트수준에서 스캔플립플롭을 선택하여야 최적화된 성능을 얻을 수 있다. 본 논문에서는 테스트용이도를 증진시키기 위해, 상위수준의 기능정보에 대해서는 테스트점을 삽입하여 제어흐름(control flow)을 변경하고, 상위 수준의 합성 후에 하위 수준에서 스캔플립플롭을 선택하여 다시 합성하는 상위.하위 수준에서 통합된 테스트 합성 기술을 제안한다. 실험결과 통합된 테스트 합성 기술이 대부분의 벤치마크 회로에서 높은 고장검출율을 보여주고 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8B
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• pp.646-656
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• 2008

In this paper, we design and verify the MAC chip of the two-stage AWG-based WDM-PON which considers 128 ONUs and 32 wavelengths. Each wavelength with the capacity of 1Gbps is allocated to ONU for downstream transmission but each wavelength for upstream transmission can be shared by four ONUs. Therefore, MAC protocol is required to avoid the collision and use the network resource efficiently among ONUs which are sharing the same wavelength. To design a request/permit-based MAC protocol, we define a unit-chip module called sub-MAC. The WDM-PON with 128 ONUs can be implemented by using 32 sub-MAC modules. The sub-MAC consists of one control unit, one receipt unit and four transmission units. The state transition diagram of the module is described by the internal/external control signals among the functional units. The function of the sub-MAC module is verified through logic simulation using ModelSIM.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.