• Nuclear Engineering and Technology
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• v.17 no.4
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• pp.247-255
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• 1985

This paper describes a new method for the design of variable structure model-following control systems(VSMFC). This design concept is developed using the theory of variable structure systems (VSS) and slide mode. The new results are presented on the sliding control methodology to achieve accurate tracking for a class of nonlinear, multi-input multi-output(MIMO), time varying systems in the presence of parameter variations. The design requires little computational effort. The dynamic response is insensitive to parameter variations. The feasibility and the advantages of the method are illustrated by applying it to a 1000 MWe boiling water reactor(BWR). The control is studied in the range of 85%∼90% of rated power for load-following control. A set of 12 nonlinear differential equations is used to simulate the total plant. A 6-th order linear model has been developed from these equations at 85% of rated power. The obtained controller is shown by simulations to be able to compensate for a plant parameter variation over a wide power range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4B
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• pp.412-421
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• 2011

An economic ship routing means to sail a ship with a goal of minimizing the fuel consumption by utilizing weather forecast information, and many such systems have been recently developed. Most of them assume that sailing is carried out with a constraint like a fixed output of engine-power or a fixed sailing speed. However, if the output of engine-power is controlled, it is possible to reduce the fuel consumption by sailing a ship under a relatively good weather condition. In this paper, we propose a novel economic ship routing system which can search optimal outputs of the engine-power for each part of a path by employing an evolutionary strategy. In addition, we develope an $A^*$ algorithm to find the shortest path and a method to enhance the degree of curve representation. These make the proposed system applicable to an arbitrary pair of departure and destination points. We compared our proposed system with another existing system not controlling output of the engine-power over 36 scenarios in total, and observed that the former reduced the estimated fuel consumption than the latter by 1.3% on average and the maximum 5.6% with little difference of estimated time of arrival.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.389-391
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• 2019

In this study, we design a remote broadcasting system that can output announcement to a remote place using wired/wireless telephone. The designed remote broadcasting system uses the LTE module to amplify the telephone voice received wirelessly through the amplifier and output it. Also, a text message for broadcasting can be sent to a remote broadcasting system through a wired/wireless telephone capable of transmitting a text message, and the remote broadcasting system that receives the broadcasting text message can automatically output the corresponding announcement stored in the voice device. For security reasons, the telephone number of the receiver is analyzed by a comparison algorithm so that only the administrator and registered users can use the system. At this time, the recorded announcement broadcast is outputted through the speaker only when it is confirmed as the registered user. The system designed in this study allows the user to output announcements quickly without being limited by time and place.

• Journal of IKEEE
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• v.24 no.4
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• pp.975-981
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• 2020

A 10 GHz LC voltage-controlled oscillator (VCO), which controls an amplitude of output signal, is proposed to improve the phase noise. The proposed amplitude control circuit for the LC VCO consists of a peak detector, an amplifier, and a current source. The peak detector is performed detecting the lowest voltage of the output signal by using two diode-connected NMOSFET and a capacitor. The proposed 10 GHz LC VCO with an amplitude control circuit for output signal is designed using a 55 nm CMOS process with a supply voltage of 1.2 V. Its area is 0.0785 ㎟. The amplitude control circuit used in the proposed LC VCO reduces the amplitude variation 242 mV generated in the output signal of the conventional LC VCO to 47 mV. Furthermore, it improves the peak-to-peak time jitter from 8.71 ps to 931 fs.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.557-565
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• 2020

In order for thermal degradationIn, excore nuclear flux monitoring system, as a monitoring and signal processing methodology of reactor power, monitors neutron pulses generated during nuclear fission as frequency status, and converts them into DC voltage, and then log values resultantly. The methods realy applied in the nuclear power plant are to construct combination of counters and flip-flops, or diodes and capacitors up to now. These methodes are reliable for relative high frequencies, while not credible for reasonable low frequencies or extreme low values. Therefore, we developed the circuit that converts frequencies into DC voltages, into and into log DC values in the wide range from low Hz to several hundred high kHz. We proved their validities through testing them using real data used in nuclear power plant and analyzed their results. And, these methods will be used to measure the neutron level of excore nuclear flux monitoring system in nuclear power plant.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.465-471
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• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of Aerospace System Engineering
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• v.14 no.5
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• pp.42-48
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• 2020

This research illustrates how the hybrid engine system comprising of a two-cycle reciprocal engine with an integrated generator and a battery is prepared for the design process. The purpose of this research is to increase flight endurance taking advantage of the high energy density of hybrid propulsion systems as well as to cope with current environmental issues by reducing fossil fuel. The hybrid system is designed to offer 6 kW power, and the power can be adjusted by controlling the engine's RPM in accordance with load variations. In addition, the battery is adopted to offer extra electric power that this hybrid system cannot cover, and can function as the main power source in limited time in the case of an emergency situation. Besides that, the generator is directly mounted on an engine crank-shaft, and in turn, they can share the same RPM. Thus, it is hypothesized that this integration method can make a compact design possible by reducing space for the installation in the fuselage of UAVs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.113-121
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• 2005

In this paper, a constant output power supply system for ozonizer is proposed to remove the noise of ozonizer and control the output of ozonizer using feedback control. The proposed system is based on the rouble control loop such as the outer voltage control loop and inner current control loop. In the proposed system overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the experimental results.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.