• The Journal of the Acoustical Society of Korea
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• v.28 no.7
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• pp.661-667
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• 2009

Trabecular-bone-mimicking phantoms consisting of parallel-nylon-wire arrays were used to investigate correlations of phase velocity and attenuation coefficient with structural properties in trabecular bone. Trabecular separation (Tb.Sp) of the 7 trabecular-bone-mimicking phantoms ranged from 300 to $900\;{\mu}m$ and volume fraction (VF) from 1.6% to 8.7%. Phase velocity and attenuation coefficient of the phantoms were measured by using a through-transmission method in water, with a matched pair of broadband unfocused transducers with a diameter of 12.7 mm and a center frequency of 1 MHz. Phase velocity and attenuation coefficient at 1 MHz decreased almost linearly with increasing Tb. Sp and increased almost linearly with increasing VF. The simple and multiple linear regression models with phase velocity and attenuation coefficient as independent vanables and Tb.Sp and VF as dependent variables demonstrated that the coefficients of determination for the prediction of VF were higher than those for the prediction of Tb.Sp. The results obtained in the trabecular-bone-mimicking phantoms consisting of parallel-nylon-wire arrays were consistent with those in human trabecular bone suggesting that the structural properties can be estimated from the measurements of phase velocity and attenuation coefficient in trabecular bone.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.262-265
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• 2012

In this paper, a Ka-band 8 W power amplifier module with WR-28 waveguide input and output ports is implemented and measured using four 2 W power amplifier modules and 4:1 waveguide power combiners with high isolation of 25 dB at 35 GHz. The 2 W power amplifier modules are fabricated using waveguide-to-microstrip transitions and show output power of 32.5~33.3 dBm and power gain of 26.9~28.7 dB at 35 GHz. Four 2 W power amplifier modules are combined through 4:1 waveguide power combiners with resistive septum and the combined power shows 39.0 dBm(8 W) under 6 V drain bias and 39.6 dBm(9.1 W) under 6.5 V drain bias at 35 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.8-14
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• 2016

High-level conceptual design analysis results of satellite communication system for Korea augmentation satellite system (KASS) satellite communication system, which is a part of KASS and consisted of KASS uplink Stations and two leased GEO is presented in this paper. We present major functions such as receiving correction and integrity message from central processing system, taking forward error correction for the message, modulating and up converting signal and conceptual design analysis for concepts for design process, GEO precise orbit determination for GEO ranging that is additional function, and clock steering for synchronization of clocks between GEO and GPS satellites. In addition to these, KASS requires 2.2 MHz for SBAS Augmentation service and 18.5 MHz for Geo-ranging service as minimum bandwidths as a results of service performance analysis of GEO ranging with respect to navigation payload(transponder) RF bandwidth is presented. These analysis results will be fed into KASS communication system design by carrying out final analysis after determining two GEOs and sites of KASS uplink stations.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.1
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• pp.27-35
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• 2013

In this paper, a compact, broadband quasi-Yagi antenna utilizing balance analysis of the ultra-wideband microstrip-to-coplanar stripline(MS-to-CPS) balun is proposed. The antenna size was reduced by removing the reflector on bottom layer and ground plane is used as a reflector. A planar balun that transforms from microstrip(MS) to balanced coplanar stripline(CPS) is characterized in the amplitude and phase imbalances at CPS output ports are investigated and discussed. As compared with the conventional balun, the proposed MS-to-CPS balun demonstrated very wideband performance from 7 to over 20 GHz. From the simulation study, amplitude and phase imbalances are within 1 dB and ${\pm}5^{\circ}$, respectively. The implemented antenna provides very wide bandwidth from 6.9 to 15.1 GHz(74.5 %). The gain of the antenna is from 3.7 to 5.5 dBi, the front-to-back ratio is more than 10 dB, and the nominal radiation efficiency is about 94 %.

• Journal of Advanced Navigation Technology
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• v.25 no.1
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• pp.68-77
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• 2021

In this paper, a GPS/MEMS IMU integrated navigation receiver module capable of operating in a high dynamic environment is designed and fabricated, and the results is confirmed. The designed module is composed of RF receiver unit, inertial measurement unit, signal processing unit, correlator, and navigation S/W. The RF receiver performs the functions of low noise amplification, frequency conversion, filtering, and automatic gain control. The inertial measurement unit collects measurement data from a MEMS class IMU applied with a 3-axis gyroscope, accelerometer, and geomagnetic sensor. In addition, it provides an interface to transmit to the navigation S/W. The signal processing unit and the correlator is implemented with FPGA logic to perform filtering and corrrelation value calculation. Navigation S/W is implemented using the internal CPU of the FPGA. The size of the manufactured module is 95.0×85.0×.12.5mm, the weight is 110g, and the navigation accuracy performance within the specification is confirmed in an environment of 1200m/s and acceleration of 10g.

• Journal of Advanced Navigation Technology
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• v.26 no.5
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• pp.365-372
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• 2022

Compared to sensors mainly used in human activity recognition (HAR) systems, inertial measurement unit (IMU) sensors are small and light, so can achieve lightweight system at low cost. Therefore, in this paper, we propose a binary neural network (BNN) based gait pattern analysis system using IMU sensor, and present the design and implementation results of an FPGA-based accelerator for computational acceleration. Six signals for gait are measured through IMU sensor, and a spectrogram is extracted using a short-time Fourier transform. In order to have a lightweight system with high accuracy, a BNN-based structure was used for gait pattern classification. It is designed as a hardware accelerator structure using FPGA for computation acceleration of binary neural network. The proposed gait pattern analysis system was implemented using 24,158 logics, 14,669 registers, and 13.687 KB of block memory, and it was confirmed that the operation was completed within 1.5 ms at the maximum operating frequency of 62.35 MHz and real-time operation was possible.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.853-861
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• 2018

This paper proposes the application of harmonic constraints to address the problems caused by abnormal voltage increases when electric railway vehicles are running. The AC line that supplies the train with power during operation is used to provide electricity of 25kV/60 Hz, but gradually the size and frequency of harmonics involved in the line are varied with the technological evolution of the railroad vehicle electrical equipment. An increase in heat losses due to the failure of the instrument transformer (PT), the main circuit device, which is a serious problem with the recent train safety operation, or to the main displacement voltage. When high frequency components are introduced through low frequency Transformers of the main circuit device, the high intensity of the components is caused by the high intensity of the core and the current flow of the parasitic core is increased, thus generating heat. To solve this problem, the recent adjustment of the sequence has applied artificial NOTCH OFF of the power converter. However, the method of receiving and controlling the OFF signal operates by interaction between the ground and the vehicle's devices, thus it is invalid in the event of failure, and an actual accident is occurring. Therefore, the harmonic currents were required to prevent possible flow of harmonics, and conducted a study to prevent accidental occurrence of train accidents and to verify feasibility of the device through the simulations of the train's experimental analysis and the simulations of the train for safe operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.