• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.2C
• /
• pp.191-200
• /
• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.61-67
• /
• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.3 no.4
• /
• pp.49-69
• /
• 2010

In this paper, we propose a class of spectrum sensing schemes for cognitive radio with receive diversity. By considering the generalized likelihood ratio test detector in each branch and exploiting non-linear diversity combining strategy, the proposed scheme exhibits reasonable performance for spectrum sensing even in the environment of heavier-tailed noise. From the results of analysis and computer simulations, it is observed that the proposed scheme provides significant performance gain and performance stability over the conventional schemes, especially in impulsive noise environment.

• Journal of Advanced Marine Engineering and Technology
• /
• v.23 no.2
• /
• pp.210-215
• /
• 1999

The proposed detector is consists of three-phase sinusoidal signal generator and peak detector. This peak detector can detect the peak voltage value at the state of variable frequency. In experi-ment three-phase sinusoidal signals are generated from D/A converter using IBM PC and deliv-ered to the peak detector. Each signals are squared by multiplier and summed up Peak value is the square root of summed value extracted by square root circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.7
• /
• pp.685-691
• /
• 2003

This paper newly analyzes the effect of the phase noise in the frequency synthesizer on the performance of SFH/M-NCFSK system by standard frequency deviation(equation omitted) when noncoherent FSK demodulation of the square-law detector is considered. We derive the SER in the SFH system and analyze the effect of phase noise on the SFH/M-NCFSK system performance according to the hopping frequency spacing (1/T$\_$h/) and the variation of the standard frequency deviation (equation omitted). The required SNR is about 13.4 dB to meet Ps=10$\^$-3/ when the standard frequency deviation is about 4.0 Hz and the hopping frequency spacing (1/T$\_$h/) in the SFH/2-NCFSK system is 30. So, there is about 2.4 dB power penalty than the phase noise-free system. If the hopping frequency spacing 1/T$\_$h/ is under 30, the error floor may happen and SER considerably grows up. We show that the analytic results closely match with the simulation results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.17 no.3
• /
• pp.26-35
• /
• 1980

The degradation of image due to the finite size of sensing devices has been one of the problems in all digital imaging systems. The basic study on the improvement of the spatial resolution was carried out in both spatial and frequency domains by the resolution recovery techniques which have been used in optics. Here, the techniques were applied to CT (Computerized Tomography) system, and image with finer resolution was obtained by these techniques. The basic theory is described and the results of the simulation are shown.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.7
• /
• pp.1407-1413
• /
• 1994

To obtain accurate target information in a radar system, clutter or interference signals must first be effectively removed for target detection. In this paper, the signal is projected onto a constrained orthogonal subspace, so that a minimum variance optimal detector is transformed into an unconstrained detector. The proposed algorithm is equivalent to the conventional optimal detector algorithm, and th algorithm structure shows that the Gram-Schmidt orthogonalization can be achieved to obtain the fast convergence. The performance of the proposed method was observed by simulation experiments.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.12
• /
• pp.2716-2724
• /
• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.1
• /
• pp.175-181
• /
• 2005

This paper proposes the fuzzy-PLL control system for fast response time and precision control of automation systems. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone, but also a long delay interval that makes a high speed operation unable. In order to solve the problems, the proposed system, which provides the improvement in terms of the control region in high speed and precision control, first used the fuzzy control method for fast response time and when the error reaches the preset value, used the PLL method designing new PFD for precision control. The new designed multi-PFD improves the dead zone, jitter noise and response characteristics, which is consists of P-PFD(Positive edge triggered PFD) and N-PFD(Negative edge triggered PFD) and can improve response characteristics to increase PFD gain.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.4 no.4
• /
• pp.247-252
• /
• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).