• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.23-28
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• 2010

We propose a reference vector diversity method in multi-cell multi-user uplink system with the subspace interference alignment to obtain higher sum rate capacity. The proposed method transmits several reference vectors before the data transmission, and selects the best reference vector to maximize the cell sum rate. The proposed method provides higher sum-rate capacity compared with the previous interferenc alignment. Simulation result exhibits the proposed method improves the sum-rate capacity by 60%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1071-1079
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• 2002

This paper reports a methodology and application lot calculating distribution of the director in a liquid crystal cell by a numerical technique. To calculate distribution of the director, we applied a three dimensional finite element method (FEM) and calculated the distributions of electric potential and director in the liquid crystal cell. We have considered the free-energy density in the bulk of liquid crystal cell and calculated the switching property by the Ericksen-Leslie equation and the Laplace equation. We have calculated the optical transmission with distribution of the director by Berreman's method and confirmed the threshold voltage and the response time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.1-9
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• 2002

The distribution characteristics of data retention time for DRAM was studied in connection with the probability distribution of the cell parameters. Using the cell parameters and the transient characteristics of cell node voltage, data retention time was investigated. The activation energy for dielectric layer growth on cell capacitance, the recombination trap energy for leakage current in the junction depletion region, and the sensitivity characteristics of sense amplifier were used as the random variables to perform the Monte Carlo simulation, and the probability distributions of cell parameters and distribution characteristics of cumulative failure bit on data retention time in DRAM cells were calculated. we found that the sensitivity characteristics of sense amplifier strongly affected on the tail bit distribution of data retention time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.26-34
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• 2002

A dynamically-allocated topographical model, so-called cell advancing model, has been developed modifying the cell model. Memory requirements are reduced by dynamically allocating completed topography and material information only at surface cells, and setting other cells as a material index. In this paper, this model is presented and verified with applications to etching process by using the analytic model and Monte Carlo model for the incident ion flux, deposition process, and process integration. In case of DRAM cell fabrication process with 5,440,500(130$\times$155$\times$270) cells takes about 22MB memory to represent the topography.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.478-484
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• 2004

In this paper, two lossless snubber cells are proposed to generalize high frequency converter with losslless snubber. The selecting of snubber cells, which generalize high frequency converters, are depended on converter topologies. The cells have a saturable inductor, LC resonant tank and two diodes. In the cells, the saturable inductors extremely reduce resonant energy in the LC resonant tank. By minimizing resonant energy, the converter, which applies snubber cells, can operate at high frequency. These cells are applied for Buck, Boost, Buck-Boost, Cuk, ZETA, and SEPIC to generalize converter which have lossless snubber. The boost type converter has been implemented, with 400 kHz switching frequency for 125 W load to verify the converter characteristics.

• Journal of IKEEE
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• v.16 no.1
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• pp.34-44
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• 2012

This paper proposes a practical compensation method by using digital signal processing over the creep error which is representative in strain gauge loadcell. The signal compensation method carry out the simulation by deciding compensation constant (time constant) and coefficient measuring the loadcell output response. Then, compensation constant and coefficient are stored on the microprocessor. By using calculated on microprocessor creep error compensation values, weighting value is showed as a digital signal by reducing error values measured through output signals of loadcell. In addition, we apply error compensation method in order to have a dedicated software for loadcell electronic scale. This technique is useful because it has great influence on error rate reduction that has been produced by conventional electronic scales (0.03%). As a result our technique gives better accuracy (0.01%~0.003%) as what is given by digital electronic scale, while it has less complex operation processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.39-44
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• 2013

Long Term Evolution (LTE) - Advanced has developed Heterogeneous Network (HetNet) that consists of a mix of macrocells and low-power nodes such as picocells to improve the system performance. Also, to encourage data offloading in HetNet, Cell Range Expansion (CRE) have been introduced. In this paper, we propose a cell selection scheme based on Signal to Interference plus Noise Ratio (SINR) for optimal offloading effect. And we manage the interference for user located in cell range expanded region using Almost Blank Subframe (ABS) with flexible ABS ratio to improve the spectrum efficiency in time domain. Simulation results show that proposed scheme can improve spectrum efficiency of macrocell and picocell user. Eventually, proposed scheme can imporve overall user performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.628-631
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• 2014

Recently, the proliferation of new applications, e.g., mobile TV, Internet gaming, large file transfer, and the various of user terminals, e.g., smart phones and notebooks, has dramatically increased user traffic and network load. In order to meet this traffic growth, vendors and cellular operators are working on the development of new technologies and cellular standards. Within them, small cell deployment has been heralded as one of most promising way to increase both coverage and capacity of future cellular network. Small cell technology enables to improve capacity of cellular radio network by tight cooperation between small cell and macro cell in multi-tier network where small cells are densely deployed within macro cell coverage. In this paper, we describe the deployment scenarios for cooperation between macro cell and small cells and state-of-the-art technologies related to dense small cell deployment. Then, we also provide design principles and standardization trends for small cell enhancement in 3GPP.