• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2262-2264
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• 2005

지금까지 변전소나 개폐소에서 전류, 전압을 계측하는 수단으로서 주로 철심과 권선으로 구성되어진 변류기(CT), 계기용 변압기(PT, PD)가 사용되어져 왔다. 최근, 2차측의 계측기나 보호 Relay의 Digital화가 진전되어 또한 이것을 Digital Network으로 총합한 Intelligent 변전소의 구축이 검토되어지고 있으며, Digital Network에 대응한 변성기 관련규격인 IEC 60044가 근래 제정되어짐에 따라 이에 적합한 전자식 변성기가 요구되어지고 있다. 상기와 같은 요구로 인해 당사에서는 IEC 60044를 기반으로 한 전자식변성기 Layout을 구성하였으며, CT는 검출부에 Rogowski Coil을 적용하며 그 후단에 적분기를 설치하였으며, VD는 검출부에 중간 전극을 이용해서 분압하는 방식인 Capacitive Voltage Divider를 사용하고 증폭기를 삽입하여, 각각 요구되는 전압 신호를 얻었다. 이러한 신형 CT/VD의 적용으로 종래의 CT/PT가 차지하는 공간이 필요없게 되어 컴팩트한 GIS의 구조가 가능하게 되어 있다.

• Annual Conference of KIPS
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• 2001.10b
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• pp.1459-1462
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• 2001

혼성 신호 회로의 설계에 있어 저비용의 고효율 테스트 효율을 보장하기 위해 테스트의 노력은 계속되어 왔다. 특히 테스트를 고려한 BIST(built-in-self-test)설계 방법으로 발전해가고 있는 추세인데, 회로상에서 전체적인 테스트 용이도와 분석에 있어 보다 향상된 방법으로 접근할 수 있고 이러한 시스템에 대해 분석하는데 수월하게 할 수도 있다. 이 논문에서는 효과적인 테스트를 위한 방법을 위해 전압 검출기를 이용한 기준 전압 DC 테스트로써 테스트시간을 감소시키고 효과적인 고장 검출률을 갖는 BIST를 구현하는 것을 제안하였다. 즉 정상적인 회로와 고장회로에서의 동작에서 전압의 파이를 검출하는 회로를 하드웨어상으로 구성함으로써 비용과 시간등을 효과적으로 줄이는 방법을 제안하였다. 실험 결과에서는 기존의 BIST와 비교하여 향상된 것을 나타낸다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.715-722
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• 2000

In this paper, the PLDRO is designed and implemented for X-band. It is comprised of tunable high Q resonator with a varactor diode for frequency tuning, loop filter and a 1/8 prescaler which up to 10GHz. Also, it is implemented a TCXO and a VCO signal into the phase detector and achieved a highly stable signal source. From the measurement, the designed PLDRO has the output power of 2.5dBm at 8GHz and phase noise of -64.33dBc at 10KHz offset from carrier. Its characteristic is 26 dBc. This PLDRO has much better temperature stability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of the Korean Society of Radiology
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• v.13 no.6
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• pp.831-840
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• 2019

The X-ray detector by liquid crystal with front light was proposed and verified by a X-ray image. The proposed detector utilizes the visible light instead of the electric signal by transistor. Therefore, it shows low noise and can be fabricated at low cost. The liquid crystal detector uses the orientation change of the liquid crystal molecule by conductivity change of the photoconductive layer. We can get the X-ray image from the transmitted light through the liquid crystal. The X-ray dose was calibrated from the measured transmittance of the visible light after comparison to the reference transmittance curve of the liquid crystal. The amorphous Se was used for photo con ducting layer and parylene was used for the liquid crystal alignment instead of the conventional alignment layer which needs high-temperature process over 200℃. The proposed X-ray detector can decrease the X-ray dose by high sensitivity which was verified by simulation. After the fabrication of the X-ray detector, the X-ray image was obtained as a function of the bias voltage to the liquid crystal. 10 lines/mm resolution was obtained from the line pattern and we will apply it to the 17inch diagonal liquid crystal X-ray detector with 3π retardation.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.247-248
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• 2011

본 논문에서는 10kW급 3상 새그전압 보상기를 구현함에 있어 필요한 알고리즘인 새그 검출기법, 양방향 싸이리스터를 통한 계통 차단, RMS 출력전압 제어기법을 논의한다. 시작품을 제작하여 실험을 거쳐 타당성 및 안정성을 검증하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• Journal of radiological science and technology
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• v.27 no.2
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• pp.45-50
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• 2004

Synthesis diamond films have been deposited on the molybdenum substrates using an microwave plasma enhanced chemical vapor deposition method. The effects of deposition time, surface morphology, infrared transmittance and Raman scattering have been studied. Diamond deposited on molybdenum substrate for 100 hours by MW plasma CVD from $CH_4-H_2-O_2$ gas mixture had good crystallity with $100[{\mu}m]$ thickness needed for radiation detector. Diamond radiation detector of M-I-M type was made and the current of radiation detector was increased by increasing X-ray dose.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.