• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2511-2517
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• 2009

Recently, a FMCW radar is used for the various purposes in the short range detection and tracking of targets. The main advantages of a FMCWradar are the comparative simplicity of implementation and the low peak power transmission characterizing the very low probability of signal interception. Since it uses the frequency modulated continuous wave for transmission and demodulation, the received beat frequency represents the range and Doppler information of targets. Detection and extraction of useful information from targets are performed in this beat frequency domain. Therefore, the resolution and accuracy in the estimation of a beat spectrum are very important. However, using the conventional FFT estimation method, the high resolution spectrum estimation with a low sidelobe level is not possible if the acquisition time is very short in receiving target echoes. This kind of problems deteriorates the detection performance of adjacent targets having the large magnitude differences in return echoes and also degrades the reliability of the extracted information. Therefore, in this paper, the model parameter estimation methods such as autoregressive and eigenvector spectrum estimation are applied to mitigate these problems. Also, simulation results are compared and analyzed for further improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.2
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• pp.254-262
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• 2016

With the increased demand for automotive radar systems, mutual interference between vehicles has become a crucial issue that must be resolved to ensure better automotive safety. Mutual interference between frequency modulated continuous waveform (FMCW) radar system appears in the form of increased noise levels in the frequency domain and results in a failure to separate the target object from interferers. The traditional fast fourier transform (FFT) algorithm, which is used to estimate the beat frequency, is vulnerable in interference-limited automotive radar environments. In order to overcome this drawback, we propose a high-resolution frequency estimation technique for use in interference environments. To verify the performance of the proposed algorithms, a 77GHz FMCW radar system is considered. The proposed method employs a high-resolution algorithm, specially the multiple signal classification and estimation of signal parameters via rotational invariance techniques, which are able to estimate beat frequency accurately.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.3
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• pp.639-648
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• 2017

Electronic warfare systems for extracting information of the threat signals can be employed under the circumstance where the power of the received signal is weak. To precisely and rapidly detect the threat signals, it is required to use methods exploiting whole energy of the received signals instead of conventional methods using a single received signal input. To utilize the whole energy, numerous sizes of windows need to be implemented in a detector for dealing with all possible unknown length of the received signal because it is assumed that there is no preliminary information of the uncooperative signals. However, this grid search method requires too large computational complexity to be practically implemented. In order to resolve this complexity problem, an approach that reduces the number of windows by selecting the smaller number of representative windows can be considered. However, each representative window in this approach needs to cover a certain amount of interval divided from the considering range. Consequently, the discordance between the length of the received signal and the window sizes results in degradation of the detection performance. Therefore, we propose the weighted energy detector which results in improved detection performance comparing with the conventional energy detector under circumstance where the window size is smaller than the length of the received signal. In addition, it is shown that the proposed method exhibits the same performance under other circumstances.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.425-431
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• 2020

Recent advancements in industries and technologies have resulted in an increase in the volume of transportation, management, and distribution of logistics. Radio-frequency identification (RFID) technologies have been developed to efficiently manage such a large amount of logistics information. The use of RFID for management is being applied not only to the logistics industry, but also to the power transmission and energy management field. However, due to the limitation of program development capacity, the RFID device is limited in development, and this limitation is vulnerable to security because the existing strong encryption method cannot be used. For this reason, we designed a chaotic system for security with simple operations that are easy to apply to such a restricted environment of RFID. The designed system is a two-dimensional tent map chaotic system. In order to solve the problem of a biased distribution of signals according to the parameters of the chaotic dynamical system, the system has a cryptographic parameter(𝜇₁), a distribution parameter(𝜇₂), and a parameter(𝜃), which is the constant point, ID value, that can be used as a key value. The designed RFID authentication system is similar to random numbers, and it has the characteristics of chaotic signals that can be reproduced with initial values. It can also solve the problem of a biased distribution of parameters, so it is deemed to be more effective than the existing encryption method using the chaotic system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.436-442
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• 2020

ESS(energy storage system) has recently become an important power source in various areas due to increased renewable energy resources. The more ESS is used, the less the effective capacity of the ESS. Therefore, it is important to manage the remaining useful lifetime(RUL). RUL can be checked regularly by inspectors, but it is common to be monitored and estimated by an automated monitoring system. The accurate state estimation is important to ESS operator for economical and efficient operation. RUL estimation model usually requires complex mathematical calculations consisting of cycle aging and calendar aging that are caused by the operation frequency and over time, respectively. A lightweight RUL estimation model is required to be embedded in low-performance processors that are installed on ESS. In this paper, a lightweight ESS RUL estimation model is proposed to operate on low-performance micro-processors. The simulation results show less than 1% errors compared to the original RUL model case. In addition, a performance analysis is conducted based on ATmega 328. The results show 76.8 to 78.3 % of computational time reduction.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.211-217
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• 2008

Recently, there are many efforts to support seamless mobility in 802.11 WLANs using IP Layer mobility protocols. The IP layer mobility protocols are the most efficient mechanism to guarantee the service session continuity when IP subnet is changed during handover. Even if the IP layer mobility protocols are quite efficient, the feature of the protocols that had been designed to consider only L3 layer makes it difficult to improve the performance of hand over more and more. Nowadays, to overcome this limitation of IP mobility protocols, many researchers have worked on the mobility protocols integration of different layers (e.g., L2 layer). In this paper, we propose the enhanced Proxy MIPv4 to minimize the latency of handover using MIH protocol in 802.11 WLANs. The proposed mechanism minimizes the latency of authentication by exchanging security keys between Access Routers during handover. Moreover, it also minimizes packet losses by Inter-AP Tunneling and data forwarding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.