• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1345-1346
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• 2007

다양한 게이트 절연막의 펜타신 박막 트랜지스터의 전기적 특성을 atomic force microscope (AFM), X-선 회절을 사용하여 분석하였다. 펜타신 박막 트랜지스터는 thermal evaporator 방법을 사용하여 여러 폴리며 기판위에 제작하였다. Hexamethylsilasane (HMDS), polyvinyl acetate (PVA), polymethyl methacrylate (PMMA)등의 폴리머 기판을 사용하여 다양한 온도에서 증착시켰다. 이 때 PMMA위에 증착시킨 펜타신의 경우가 가장 큰 그레인 크기를 보였고, 가장 적은 트랩 농도를 보였다. 그리고 상부 전극 구조를 가진 박막 트랜지스터를 HMDS 처리를 한 $SiO_2$와 PMMA 절연막을 사용하여 제작하고 비교하였다. 이때 PMMA기판 위에 제작한 트랜지스터는 전계효과 이동도가 ${\mu}_{FET}=0.03cm^{2}/Vs$ 이고, 문턱이전 기울기 0.55V/dec, 문턱전압 $V_{th}=-6V$, on/off 전류비 $>10^5$의 전기적 특성을 보였고, $SiO_2$ 기판위에 제작한 트랜지스터는 전계효과 이동도 ${\mu}_{FET}=0.004cm^{2}/Vs$, 문턱이전 기울기 0.518 V/dec, 문턱전압 $V_{th}=5V$, on/off 전류비 $>10^4$의 전기적 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.454-456
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• 2017

Current and capacitance-voltage characteristics of tunnel field effect transistor (TFET) with various quantum models were investigated. Density gradient, Bohm quantum potential (BQP), and Vandort quantum correction are used with calibrating against Schrodinger-Poisson model. Drive-currents in all models. are decreased. When only BQP is used, SS and $V_{onset}$ are fixed but drive-current is decreased 3 times more than those of no quantum model. And When BQP with Vandort and density gradient are used, SS increased more than 40 mV./dec and $V_{onset}$ shifted as 0.07 eV.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.11
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• pp.84-91
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• 2006

Recently, all the electrical parts for satellite application are required more strong against cosmic rays, because spacecraft's life time and function are depending on the their conditions. Also, a TID effect test was undertaken with units and/or subsystems which are already assembled on the PCB in past time. However, it is very hard to know and analyze that some abnormal states are appeared after launch. Moreover, it is necessary to perform a test of TID effects based on the parts level for preparing preliminary data in cosmic rays. Therefore, this paper presents a test-bed to perform a TID effect test of Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) which is a fundamental element for electronics.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.193-194
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• 2012

그래핀(graphene)은 탄소원자가 육각형 벌집 모양 배열의 격자구조를 가지는 원자 한층 두께의 이차원 물질이다. 그래핀은 전도띠(conduction band)와 가전자띠(valence band)가 한 점에서 만나고 에너지와 역격자의 k 벡터가 선형적으로 비례하는 에너지 구조를 가진다. 이로 인해 그래핀은 매우 빠른 전하 이동도를 가지며 원자 한 층의 두께임에도 불구하고 약 2.3%의 빛을 흡수할 수 있으며 자외선 영역부터 적외선 영역까지의 넓은 파장대의 빛을 흡수 할 수 있다. 이와 같은 그래핀의 우월한 성질을 이용하면 광 응답에 고속으로 반응하고 높은 주파수의 광통신에서도 작동 할 수 있는 그래핀 광소자를 제작할 수 있게 된다. 하지만 미래의 고속 그래핀 광소자를 실현하기에 앞서 그래핀의 광응답에 대한 정확한 이해가 필요하다. 그리하여 본 연구에서는 그래핀 광소자를 제작하고 광소자의 광응답 전기적 성질을 분석하여 그래핀의 광응답 특성을 얻어내고자 실험을 진행하였다. 그래핀을 채널 물질로 하고 소스, 드레인, 후면 게이트를 가지는 일반적인 그래핀 전계효과 트랜지스터(field-effect transistor)를 제작하고 채널에 빛을 비추고 비추지 않은 상태에서의 전기적 성질을 측정하고 그 때 얻어진 그래프의 광응답의 원인을 조사하였다. 이 때 얻어지는 $I_D-V_G$ 그래프가 광 조사 시 왼쪽으로 이동하게 되는데 이의 원인을 각 게이트 전압 구간별로 $I_D$-t 그래프를 획득하여 분석하였다. 또한 광원에 펄스를 인가하여 펄스 형태의 광원을 그래핀 전계효과 트랜지스터에 조사시키고 이에 따른 전기적 성질 변화를 관찰하였다 이 때 다양한 게이트 전압이 인가된 상태에서 레이저 펄스 광원에 의한 광전류를 검출하였으며 이를 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.179-183
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• 2012

The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.28-34
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• 2011

In previous reports, we investigated a selective assembly method of fabricating single-walled carbon nanotubes (SWCNTs) on a silicon-dioxide ($SiO_2$) surface by using only a photolithographic process. In this paper, we have fabricated field effect transistors (FETs) with SWCNT channels by using the technique mentioned above. Also, we have electrically measured gating effects of these FETs under different source-drain voltages ($V_{SD}$). These FETs have been fabricated for sensor applications. Photoresist (PR) patterns have been made on a $SiO_2$-grown silicon (Si) substrate by using a photolithographic process. This PR-patterned substrate have been dipped into a SWCNT solution dispersed in dichlorobenzene (DCB). These PR patterns have been removed by using aceton. As a result, a selectively-assembled SWCNT channels in FET arrays have been obtained between source and drain electrodes. Finally, we have successfully fabricated 4 FET arrays based on SWCNT-channels by using our simple self-assembly technique.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.168-174
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• 2006

We investigated field-effect ion-transport devices based on carbon nanotubes by using classical molecular dynamics simulations under applied external force fields, and we present model schematics that can be applied to the nanoscale data storage devices and unipolar ionic field-effect transistors. As the applied external force field is increased, potassium ions rapidly flow through the nanochannel. Under low external force fields, thermal fluctuations of the nanochannels affect tunneling of the potassium ions whereas the effects of thermal fluctuations are negligible under high external force fields. Since the electric current conductivity increases when potassium ions are inserted into fullerenes or carbon nanotubes, the field effect due to the gate, which can modify the position of the potassium ions, changes the tunneling current between the drain and the source.

• Journal of Adhesion and Interface
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• v.24 no.3
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• pp.100-104
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• 2023

Van der Waals heterostructures have garnered significant attention in recent research due to their excellent electronic characteristics arising from the absence of dangling bonds and the exclusive reliance on Van der Waals forces for interlayer coupling. However, most studies have been confined to fundamental research employing the Scotch tape (mechanical exfoliation) method. We fabricated Van der Waals vertical heterojunction transistors to advance this field using materials exclusively grown via chemical vapor deposition (CVD). CVDgrown graphene was patterned through photolithography to serve as electrodes, while CVD-grown MoSe₂ was employed as the pickup/transfer material, resulting in the realization of Van der Waals heterojunction transistors with interlayer charge transfer effects. The electrical characteristics of the fabricated devices were thoroughly examined. Additionally, we observed variations in the transistor's performance based on the presence of defects in MoSe₂ layer.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.12-16
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• 2000

The electrical characteristics of n-channel LDD structured poly-Si TFT's have been systematically investigated. It have been found that the LDD regions act as the effect of series resistance and reducing the electric field. Kink effect is disappeared and off current is greatly reduced, while on current is slightly reduced. On/off current ratio graph shows that LDD device's switching characteristic is better than that of conventional device. As a result of study, it is concluded that the effect of electric field's reduction is more dominant than that of series resistance.