• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Proceedings of the KAIS Fall Conference
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• 2012.05b
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• pp.613-616
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• 2012

자동차 시장에서 늘어나는 전장부품으로 인하여 배터리 사용이 급증함에 따라 차량용 배터리가 암전류로 인하여 방전되는 사고가 급증하고 있다. 암전류로 인한 배터리 방전을 방지하기 위해 홀효과를 이용한 저전류 센서 마그네틱 Core를 개발한다. 본 논문은 Maxwell 전자기장 해석 툴을 이용하여 마그네틱 Core의 Airgap 위치와 간격 그리고 두께를 변수로 시뮬레이션을 하였다. 시뮬레이션 결과 저전류에서 기존의 홀효과를 이용한 전류 센서보다 높은 자속밀도가 발생하는 최적의 마그네틱 코어를 설계하였고 시제품을 제작하여 시뮬레이션 결과와 실제 실험결과를 비교분석 하였다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.29-32
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• 1998

The low level leakage currents in silicon oxides were investigated. The low level leakage currents were composed of a transient component and a do component. The transient component was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The do component was caused by trap assisted tunneling completely through the oxide. The low level leakage current was proportional to the number of traps generated in the oxides. The low level leakage current may be a trap charging and discharging current. The low level leakage current will affect data retention in EEPROM.

• Journal of Sensor Science and Technology
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• v.11 no.2
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• pp.111-117
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• 2002

In this paper, we proposed calibration techniques to improve measurement accuracy in the characteristic analysis system for semiconductor devices. Systematic errors can be reduced using proposed calibration techniques. Also, error current reduction procedures including leakage current and offset current are proposed to measure low-level current in pA level. Calibration parameters are calculated and stored by microprocessor using least-square fitting with measured sample data. During measurement time microprocessor corrects measured data using stored calibration parameters. Experimental results show that current measurement error above nA level is less than 0.02%. And they also show that current measurement in pA level can be performed with about 0.2% accuracy.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.10-21
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• 2006

We have studied the characteristics of oxide VCSELS when their off-current and on-current are kept small in order to find out the possibility of low current operation. A large signal equivalent circuit model has been used. By comparing measured data and simulation results, the parameters of the large signal models are obtained including the capacitances. Using the large signal model, we have investigated the effects of capacitance and on/off currents upon the turn-on/turn-off characteristics and eye diagram. According to the experiment and simulation, the depletion capacitance, which has been neglected, is found to have significant influence on the him-on delay and eye-diagram. Therefore, for high speed and low current operation, the reduction of the depletion capacitance is essential.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.917-922
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• 2010

In this paper, a new temperature-insensitive CMOS dual-mode current reference for low-voltage low-power mixed-mode circuits is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature(PTAT) current and a complementary to absolute temperature(CTAT) current. The temperature insensitivity was achieved by the mobility and the other which is inversely proportional to mobility. As the results, the temperature dependency of output currents was measured to be $0.38{\mu}A/^{\circ}C$ and $0.39{\mu}A/^{\circ}C$, respectively. And also, the power dissipation is 0.84mW on 2V voltage supply. These results are verified by the $0.18{\mu}m$ n-well CMOS parameter.