• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.4
• /
• pp.231-239
• /
• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.755-758
• /
• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Journal of the Korea Society for Simulation
• /
• v.17 no.4
• /
• pp.199-208
• /
• 2008

Lately, since Complementary Metal Oxide Semiconductor(CMOS) image sensor system has low power, low cost and been miniaturized, hardware and applied software studies using these strengths are being carrying on actively. However, the products equipped with CMOS image sensor based polling method yet has several problems in degree of completeness of applied software and firmware, compared with hardware’s. CMOS image sensor system has an ineffective synchronous problem due to superfluous message exchange. Also when a sending of data is delayed continually, overhead of re-sending is large. So because of these, it has a problem in structural stability according to Polling Method. In this study, polling cycle was subdivided in high-speed synchronization method of firmware -based through MCU and synchronization method of Stepwise was proposed. Also, re-connection and data sending were advanced more efficiently by using interrupt way. In conclusion, the proposed method showed more than 20 times better performance in synchronization time and error connection. Also, a board was created by using C328R board of CMOS image sensor-based and ATmega128L which has low power, MCU and camera modules of proposed firmware were compared with provided software and analyzed in synchronization time and error connection.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.4 no.4
• /
• pp.342-348
• /
• 1999

This paper describes a low-cost single-phase active power filter, which consists of a half-bridge P\A미1 inverter with a s simple control circuit. In order to verify the performance of proposed active power filter, many computer simulations w with EMTP codes and experimental works with a hardware prototype were done. Both results confirm that the p proposed active power filter shows excellent performance to eliminate the harmonics generated in the single-phase non l linear‘ load. The active power filter has advantage of low implementation cost and compact size. using a half-bridge i inverter and a simple control circuit with only one current sensor. So. it can be fabricated as a plug-in type.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.49-54
• /
• 2005

This paper proposes the low power MDCT algorithm for precise FV with minimum size of sub-window in mobile phone. Proposed algerian uses the coefficient at the middle of whole result process requiring the least number of calculations, since it has a good characteristic when used as standard of the FV and needs minimum amount of operation. In addition, using the DCT result related to the middle frequency makes the characteristic of FV more superior because it suppresses the impulsive noise and difference of focus values is larger than any others. The proposed algorithm is implemented using Verilog HDL and verified using Excalibur-ARM board.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.39-48
• /
• 2009

Human face tracking has gradually become an important issue in applications for portable multimedia devices such as digital camcorder, digital still camera and cell phone. Current embedded face tracking software implementations lack the processing abilities to track faces in real time mobile video processing. In this paper, we propose a power efficient hardware-based face tracking architecture operating in real time. The proposed system was verified by FPGA prototyping and ASIC implementation using Samsung 65nm CMOS process. The implementation result shows that tracking speed is less than 8.4 msec with 150K gates and 20 mW average power consumption. Consequently it is validated that the proposed system is adequate for portable multimedia device.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.1
• /
• pp.1-9
• /
• 2007

Since data caches used in modern embedded processors consume significant fraction of total processor power up to 40%, embedded processors need power-efficient high performance data caches. This paper proposes a prefetching data cache structure which pursuing low power consumption. We added tag history table on existing data cache structure which includes hardware unit for data prefetching so that reduce the number of parallel lookup on tag memory. This strategic cache structure remarkably reduces power consumption for parallel tag lookup. Experimental results show that the proposed cache architecture induce low power consumption while maintain the same cache performance.

• Journal of Korea Multimedia Society
• /
• v.9 no.8
• /
• pp.963-970
• /
• 2006

In this paper, we proposed a motion picture processor for using low-cost color super twisted nematic liquid crystal display(CSTN-LCD). The proposed processor apply a new driving scheme using SFP(Subgroup Frame Pattern), so we extends gray scale and eliminates flicker phenomenon. In addition, we apply the BFI (Black Field Insertion) to the design compensated for response time of a LC (Liquid Crystal). We use an edge enhancement and interpolation method to improve image quality of motion picture. The hardware architecture of proposed processor has been implemented and verified on a prototype FPGA board. The proposed method can be used in the display devices such as PDA(Personal Digital Assistants), mobile phone, and PMP(Portable Multimedia Player).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.91-97
• /
• 2004

A digital over-sampling noise-shaping coder to achieve the processing accuracy for the audio signal bandwidth is designed. In order to implement an optimized design of the noise-shaping coder as a form of U (intellectual property), circuit design techniques that optimize the multiplication and the ROM architectures are proposed with emphasis on the low-voltage operation under 2.0 V and the minimization of the hardware resources. In the design and verification methodology, the overall architectures and the internal bit width have been determined through behavioral simulations. The overall performances including timing margin have been estimated through transistor-level simulations. Furthermore, the test results of the implemented chip using a 0.35-${\mu}{\textrm}{m}$ standard CMOS process proposed the validity of the proposed circuits and the design methodology.

• 한국HCI학회:학술대회논문집
• /
• 2009.02a
• /
• pp.615-619
• /
• 2009

A real-time, continuous-scale image interpolation method is proposed based on bi-linear interpolation with directionally adaptive low-pass filtering. The proposed algorithm has been optimized for hardware implementation. The original bi-linear interpolation method has blocking artifact. The proposed algorithm solves this problem using directionally adaptive low-pass filtering. It can also solve the severely problem by selection choosing low-pass filter coefficients. Therefore the proposed interpolation algorithm can realize a high-quality image scaler for various imaging systems, such as digital camera, CCTV and digital flat panel display, to name a few.