Journal of the Institute of Electronics Engineers of Korea CI (전자공학회논문지CI)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Reducing Power Consumption of Data Caches for Embedded Processors

임베디드 프로세서를 위한 선인출 데이터캐시의 저전력화 방안

  • Moon, Hyun-Ju (Department of Computer Science, Namseoul University) ;
  • Jee, Sung-Hyun (Information Strategy Team, Korea Employment Information Service)
  • 문현주 (남서울대학교 컴퓨터학과) ;
  • 지승현 (한국고용정보원 정보화전략팀)
  • Published : 2007.01.25
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Abstract

Since data caches used in modern embedded processors consume significant fraction of total processor power up to 40%, embedded processors need power-efficient high performance data caches. This paper proposes a prefetching data cache structure which pursuing low power consumption. We added tag history table on existing data cache structure which includes hardware unit for data prefetching so that reduce the number of parallel lookup on tag memory. This strategic cache structure remarkably reduces power consumption for parallel tag lookup. Experimental results show that the proposed cache architecture induce low power consumption while maintain the same cache performance.

임베디드 프로세서는 총 에너지소모량 가운데 대략 40% 이상을 캐시에서 소모하고 있으므로 에너지-효율적 고성능 데이터 캐시 구조를 필요로 한다. 본 논문에서는 임베디드 프로세서를 위한 저전력 선인출 데이터캐시 구조를 제안하였다. 제안한 데이터캐시 구조는 선인출장치(prefetching unit)를 포함한 기존 데이터캐시 구조에 태그히스토리 테이블(tag history table)을 구비함으로써 요구인출 및 선인출시 발생하는 태그메모리 병렬탐색 횟수를 감소시켰다. 이와 같은 전략적인 캐시 구조는 적은 하드웨어 비용으로 병렬탐색을 위한 전력소모를 현저히 줄일 수 있다. 실험을 통하여 제안한 데이터캐시 구조가 기존 선인출 데이터캐시 구조와 동일한 성능을 유지하면서 낮은 전력을 요구함을 확인하였다.

Keywords

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