• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.417-419
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• 2009

최근 가정내에 가전기기들을 무선으로 제어할 수 있는 홈 네트워킹이 많이 발전하는 추세에 있을 뿐만 아니라 연구가 활발히 진행되고 있다. 무선 홈 네트워킹은 기존의 유선에 비해 배선에 따른 비용 절감과 사용자의 편의로 가정내에 용이하게 적용할 수 있다. 본 연구에서는 각 센서 노드들로부터 수집된 정보들을 저전력, 저비용의 장점과 홈 네트워킹의 적합한 Zigbee 통신을 이용하여 구현하였다. 무선 센서 네트워크를 통해 온도, 습도, 조도등과 같은 환경 데이터를 사용자 개개인의 선호도에 따라 가정내에 가전기기들을 자동 설정 제어하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.23-32
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• 2005

The automatic generation of circuit diagrams has been practically used in the HDL based design for decades. Nevertheless, the diagrams became too complicated for the designers to identify the signal flows in the RTL and system level designs. In this paper, we propose four techniques to enhance the roadability of the complicated diagrams. They include i) the transformation of repetitive instances and terminals into vector forms, ii) an improved loop breaking algorithm, iii) a flat tap which simplifies the two level bus ripping structure that is required for the connection of a bundle net to multiple buses, and iv) the identification of block strings, and alignment of the corresponding blocks. Towards validating the proposed techniques, the diagrams of an industrial strength design m generated. The complexity of the diagrams has been reduced by up to $90\%$ in terms of the number of wires, the aggregate wire length, and the area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.56-64
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• 2007

We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.351-358
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• 2016

An Electrical Point Machine (NS:New-type Switch), which is equipped and operated at railways in Korea, has been used since the 1960s after being imported from Japan. On the other hand, although the mechanical configuration has improved the position motor control circuit, the electrical connection has not been improved, so NS may have a problem, such as the interlocking system of automatic train operation. In addition, NS is the most vulnerable part in the railway system and a huge train accident may occur due to minor defects. The existing NS wiring set of the circuit controller should be checked only if fixed. Therefore, an excessive inspection time only by a Railroad Signal expert is required. In this paper, the improvement of electrical connection in a NS wiring set, such as the position motor control circuit, was developed and the prototype was installed at Seoul Metro in the distance to go section. The results can be used to help make appropriate adjustments. The improvement of the NS wiring set enhance the maintenance efficiency, passenger service and the stability of the signal system as well as reducing the maintenance cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1653-1659
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• 2013

In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

• The Journal of the Korea Contents Association
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• v.17 no.11
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• pp.303-311
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• 2017

Safety accidents in railway work continue to increase every year; Engineer's negligence, trackside worker's sensory deprivation and signalman's mistake are the main reasons of such incidents. We consider this problem by far the most urgent matter in railway work because of its steady increase and risk of taking a person's life. Based on that account, a new alarm system has developed, that is called Railway Access Alarm System, to allow railway workers to sense the access of trains with not only vision, but also hearing. The detector device of this system is installed on both sides of the track locating 1.5km from the workplace. When the train enters the place, the detector device can sense the entering, sending the detect sign of train to the alarm unit, then the alarm unit warns the workers by the LED lighting and sirens. This system has several advantages compared to previous systems. First, it recognizes the train at a long distance. Secondly, there is no need for wiring work since it is a wireless system. At last, the system works by rechargeable batteries and solar charger so that it is installed in the work places where there is no external power supply. Moreover, it is proven that the system is 100% reliable by the successful on-the spot inspection evaluating the capability.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.37-39
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• 2001

반도체 설계는 급속한 기능 추가와 기가 헬쯔에 육박하는 고속 동작에 부응하는 제품의 설계와 빠른 출시를 위하여 다방면의 연구를 거듭하고 있다. 하지만, 인터넷과 정보 가전의 모바일 기기에서 요구하는 폭발적인 기능의 추가와 가전기기의 최소화를 위하여서는 그 요구를 감당하지 못하고 있다. 이를 위한 방안으로 설계 재활용과 System-On-Chip의 설계가 수년 전부터 대두되었으나 아직 큰 실효를 거두지 못하고 있다. SoC설계는 다기능을 한 칩에 구성하는 방법을 시도하고 있고, 설계 재활용은 기존의 설계(IP)를 다른 것과 혼합하여 필요한 기능을 제공하는 방법이 시도되고 있다. 이 두가지의 VLSI 설계 방식 흐름을 가능하도록 하기 위한 연구로써, 레이아웃 이식에 관한 연구를 진행하였다. IP 재활용을 위하여서는 다양한 공정변화에 신속히 대응하고, 기존의 설계 설계규칙으로 설계된 면을 현재의 공정인 0.25um, 0.18um 테크놀러지에 맞도록 변환하는 VLSI 소프트웨어 시스템을 필요로 한다. 레이아웃 설계도면을 분석하여 소자 및 배선을 인식하는 알고리즘을 연구와 개발하고, 도면을 첨단 테크놀러지의 설계 규칙에 부응하도록 타이밍, 소비 전력, 수율을 고려한 최적의 소자 및 배선의 크기를 조절하는 방법을 고안하며, 칩 면적을 최적화할 수 있는 컴팩션 알고리즘을 개발하여 레이아웃 설계 도면을 이식할 수 있는 자동화 소프트웨어 시스템을 연구하였다. 더불어, 현재 반도체 소프트웨어 시스템의 최대 문제점에 해당하는 처리 속도와 도면의 처리 능력을 비교, 검토하여 본 연구가 속도면에서 평균 27배 효율면에서 3배 이상의 상대우위를 점하였다.전송과 복원이 이루어질 것이다.하지 않은 경우 단어 인식률이 43.21%인 반면 표제어간 음운변화 현상을 반영한 1-Best 사전의 경우 48.99%, Multi 사전의 경우 50.19%로 인식률이 5~6%정도 향상되었음을 볼 수 있었고, 수작업에 의한 표준발음사전의 단어 인식률 45.90% 보다도 약 3~4% 좋은 성능을 보였다.으로서 hemicellulose구조가 polyuronic acid의 형태인 것으로 사료된다. 추출획분의 구성단당은 여러 곡물연구의 보고와 유사하게 glucose, arabinose, xylose 함량이 대체로 높게 나타났다. 점미가 수가용성분에서 goucose대비 용출함량이 고르게 나타나는 경향을 보였고 흑미는 알칼리가용분에서 glucose가 상당량(0.68%) 포함되고 있음을 보여주었고 arabinose(0.68%), xylose(0.05%)도 다른 종류에 비해서 다량 함유한 것으로 나타났다. 흑미는 총식이섬유 함량이 높고 pectic substances, hemicellulose, uronic acid 함량이 높아서 콜레스테롤 저하 등의 효과가 기대되며 고섬유식품으로서 조리 특성 연구가 필요한 것으로 사료된다.리하였다. 얻어진 소견(所見)은 다음과 같았다. 1. 모년령(母年齡), 임신회수(姙娠回數), 임신기간(姙娠其間), 출산시체중등(出産時體重等)의 제요인(諸要因)은 주산기사망(周産基死亡)에 대(對)하여 통계적(統計的)으로 유의(有意)한 영향을 미치고 있어 $25{\sim}29$세(歲)의 연령군에서, 2번째 임신과 2번째의 출산에서 그리고 만삭의 임신 기간에, 출산시체중(出産時體重) $

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.6
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• pp.59-68
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• 2022

We propose the vehicle maintenance support system to alarm consumable replacement reminders to the vehicle owner. Since the delayed replacement of the consumables makes the condition of the vehicle worse, it is crucial to replace consumables in a recommended period. The vehicle maintenance support system alarms the replacement time, which is set by the vehicle owner, based on the mileage of the installed vehicle. It integrates speed information acquired from the Controller Area Network interface for communication between Electronic Control Unit and instrument panel, exposed at the On Board Diagnostics-II port, to calculate the vehicle mileage. By this, there is no additional wiring required for the system. We verify the system has only 0.28% error by comparing the mileage on the system with the instrument cluster on the vehicle. It automatically enters low-power mode consuming 15mW, which is a negligible amount for the typical conditions of the car, to prevent the vehicle battery from discharging when the ignition is off.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1240-1252
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• 1996

In this paper we propose a layout editor for the functional module generation in the Sea-of Gates(SOG) lay-out style. The proposed layout editor provides interactive was of designing a functional module to the designer so that the layout result is very satisfiable. Especially, the editor is independent on the shape of the basic cells in the gate array template, and provides semi-automatic layout methods as well as hand layout. It also has several special functions which are not able to find in other layout tools for the module generation, and hence the designer can generate modules very fast. The layout editors implemented in C language with X-win-dow Motif environment. When we compare our editor with the previous layout editor Seadali, the design time is reduced by a factor of two for several benchmark circuits.