Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Automatic generation of higher level design diagrams

상위 수준 설계 도면의 자동 생성

  • Lee, Eun-Choul (Department of Electronic Engineering University of Incheon) ;
  • Kim, Kyo-Sun (Department of Electronic Engineering University of Incheon)
  • 이은철 (인천대학교 전자공학과) ;
  • 김교선 (인천대학교 전자공학과)
  • Published : 2005.11.01
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Abstract

The automatic generation of circuit diagrams has been practically used in the HDL based design for decades. Nevertheless, the diagrams became too complicated for the designers to identify the signal flows in the RTL and system level designs. In this paper, we propose four techniques to enhance the roadability of the complicated diagrams. They include i) the transformation of repetitive instances and terminals into vector forms, ii) an improved loop breaking algorithm, iii) a flat tap which simplifies the two level bus ripping structure that is required for the connection of a bundle net to multiple buses, and iv) the identification of block strings, and alignment of the corresponding blocks. Towards validating the proposed techniques, the diagrams of an industrial strength design m generated. The complexity of the diagrams has been reduced by up to $90\%$ in terms of the number of wires, the aggregate wire length, and the area.

회로도면 자동생성 분야는 지난 수십 년간 HDL기반 설계과정에서 사용되어 왔다. 그러나 회로 도면은 더욱 복잡해져서 레지스터 및 시스템 레벨에서 자동 생성된 회로도면을 보고 신호의 흐름을 파악하기 어렵다. 이와 같이 복잡해진 회로도면의 가독성을 향상시키기 위해 본 논문에서는 4가지 기법, 즉 i ) 심볼이나 터미널들과 같이 반복되는 회로 패턴을 벡터 형태로 치환, ii) 피드백 루프 절단 알고리즘 개선, iii) 번들 네트 생성시 발생하는 다단 연결을 간결 화할 수 있는 압축 탭, iv) 연결도에 따라 블록열을 구분하고 정렬하는 알고리즘을 제안한다. 제안된 회로도면 생성 기법의 효용성을 확인하기 위해 도면 자동생성 프로그램을 개발하고, 계층적으로 설계된 미디어 프로세서의 다양한 모듈의 도면을 생성시켰다. 실험한 결과 도면 면적을 비롯하여 배선 수, 길이 등을 $90\%$까지 감소시키고 가독성을 높이는 효과를 보였으며 블록의 분산 및 빈 공간 발생을 억제하는 효과를 보였다.

Keywords

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