Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Automatic Visual Architecture Generation System for Efficient HDL Debugging

효율적인 HDL 디버깅을 위한 아키텍쳐 자동 생성 시스템

  • Moon, Dai-Tchul (Department of Information & Communication Eng., Hoseo University) ;
  • Cheng, Xie (Department of Information & Communication Eng., Hoseo University) ;
  • Park, In-Hag (Department of Information & Communication Eng., Hoseo University)
  • Received : 2013.02.14
  • Accepted : 2013.05.10
  • Published : 2013.07.31
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Abstract

In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

본 논문은 Verilog HDL이나 VHDL로 설계된 디지털 회로의 구조를 효율적으로 분석하고 디버깅 할 수 있는 ECAD 소프트웨어를 제안한다. 이 소프트웨어는 HDL 코드를 파싱하여 내부 구조에 대한 정보를 추출한 후 여러 가지 종류의 그래픽 도우미 예를 들면, 배치배선 알고리즘을 적용하여 생성된 계층구조의 논리회로도, 각 모듈을 구성하는 요소들을 나타내는 객체 나무 그래픽, 인스턴스들의 계층구조를 나타내는 인스턴스 나무 그래픽, 내부 시그널 간의 관계를 나타내는 시그널 관계도(SPD, signal propagation diagram) 등으로 표현된다. 디버깅에 가장 중요한 기능은 여러 가지 다른 관점의 설계 정보(HDL 코드, 객체 나무, 인스턴스 나무, SPD, 파형 등)에서 임의의 객체로부터 출발하여 동일한 설계 정보를 찾아내는 기능이다. 이러한 기능들은 설계자가 수작업으로 HDL 코드를 분석하고 버그를 찾아내는 기능을 효율적으로 수행할 수 있도록 돕는다.

Keywords

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