• Journal of KIISE:Computing Practices and Letters
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• v.12 no.4
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• pp.264-274
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• 2006

Recently, a variety of organizations including enterprises tend to try to use reporting tools as a data analysis tool for decision making support because reporting tools are capable of formatting data flexibly. Traditional reporting tools have thin-client structure in which all of dynamic documents are generated in the server side. This structure enables reporting tools to avoid repetitive process to generate dynamic documents, when many clients intend to access the same dynamic document. However, generating dynamic documents for data analysis doesn't consider a number of potential readers and increases requests to the server by making clients input various parameters at short intervals. In the structure of the traditional reporting tools, the increase of these requests leads to the increase of processing load in the server side. Thus, we present the reporting tool that can generate dynamic documents at the client side. This reporting tool has a processing mechanism to deal with a number of data despite the limited memory capacity of the client side.

• Journal of KIISE:Software and Applications
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• v.30 no.1_2
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• pp.129-139
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• 2003

The PC cluster architecture is considered as a cost-effective alternative to the existing supercomputers for realizing a high-performance information retrieval (IR) system. To implement an efficient IR system on a PC cluster, it is essential to achieve maximum parallelism by having the data appropriately distributed to the local hard disks of the PCs in such a way that the disk I/O and the subsequent computation are distributed as evenly as possible to all the PCs. If the terms in the inverted index file can be classified to closely related clusters, the parallelism can be maximized by distributing them to the PCs in an interleaved manner. One of the goals of this research is the development of methods for automatically clustering the terms based on the likelihood of the terms' co-occurrence in the same query. Also, in this paper, we propose a method for duplicate distribution of inverted index records among the PCs to achieve fault-tolerance as well as dynamic load balancing. Experiments with a large corpus revealed the efficiency and effectiveness of our method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.61-70
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• 2015

This study, under the assumption that there may be a difference in colours recognized depending on background lightness and colour stimulus size, applied background lightness in a differential way and conducted an experiment by comparing the sizes of stimuli equivalent to $2^{\circ}$ and $10^{\circ}$. Based on the results, by reflecting the results of this experiment as a difference in colour recognition, which may occur when the input image is converted from a large-sized screen to a mobile-sized screen, power efficiency, one of the biggest issues, can be reflected in mobile devices and may contribute to effective three-dimensional image reproduction and image quality in 3-D or hologram as well as 2-D images.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.79-89
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• 1984

In this paper we present development of microprocessor-based 8-channel statistical multiplexer (SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.31-39
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• 2005

This paper presented new biometrics data transfer model, and use MD5 (Message Digest5) and RSA (Ron Rivest, Adi Shamir, Len Adleman) algorithm to improve biometrics data's security. So, did so that can run user authentication more safely. That is, do so that may input fingerprint among biometrics through client, and transmit processed fingerprint to server. When fingerprint information is transmitted, it uses MD5 algorithm to solve problem that get seized unlawful living body information from outside and information does Digest. And did to pass through process that transmit again this by RSA method. Also, experimented general text data and living body data that is not encoded, transmission speed and security of living body data that encoding and transmit each comparison. By running user authentication through such improved method, is expected to be applied in several. fields by method to simplify certification procedure and is little more correct and stable.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.875-885
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• 2010

CBR (Case-Based Reasoning) is a technique to infer the relationships between existing data and case data, and the method to calculate similarity and Euclidean distance is mostly frequently being used. However, since those methods compare all the existing and case data, it also has a demerit that it takes much time for data search and filtering. Therefore, to solve this problem, various researches have been conducted. This paper suggests the method of SE(Speed Euclidean-distance) calculation that utilizes the patterns discovered in the existing process of computing similarity and Euclidean distance. Because SE calculation applies the patterns and weight found during inputting new cases and enables fast data extraction and short operation time, it can enhance computing speed for temporal or spatial restrictions and eliminate unnecessary computing operation. Through this experiment, it has been found that the proposed method improves performance in various computer environments or processing rate more efficiently than the existing method that extracts data using similarity or Euclidean method does.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1738-1743
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• 2017

This paper presents an efficient image stitching method using preprocessing in order to generate a super resolution image. Two-dimensional (2D) scanners are consistently used in various areas but they have limitations such as paper sizes and materials. To overcome these problem with low-cost, an efficient imaging stitching method is proposed for producing a super resolution panorama image. To scan a very large sized paper using mobile phones, a simple portable cradle which fixes height is employed producing an input image set. To improve matching performance, a preprocessing method is introduced before searching correspondences. Then alpha blending is applied to an input image set to produce a super resolution panorama image. The proposed method is faster and easier than the existing method which is employed by Open CV. Experiment results show that the proposed method is three times faster and performs better than the existing method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.13-20
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• 2015

In this paper, we propose an algorithm that can recognize not only the number of stretched fingers but also determination of attached fingers for extracting features required for hand gesture recognition. The proposed algorithm detects the hand area in the input image by the skin color range filter based on a color model and labeling, and then recognizes various hand gestures by extracting the number of stretched fingers and determination of attached fingers using curvature information extracted from outlines and feature points. Experiment results show that the recognition rate and the frame rate are similar to those of the conventional algorithm, but the number of gesture cases that can be defined by the extracted characteristics is about four times higher than the conventional algorithm, so that the proposed algorithm can recognize more various gestures.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.73-82
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• 2014

The LM algorithm is used in solving the least square problem in a non linear system, and is used in various fields. However, in cases the applied field's target functionis complicated and high-dimensional, it takes a lot of time solving the inner matrix and vector operations. In such cases, the LM algorithm is unsuitable in embedded environment and requires a hardware accelerator. In this paper, we implemented the LM algorithm in hardware. In the implementation, we used pipeline stages to divide the target function operation, and reduced the period of data input of the matrix and vector operations in order to accelerate the speed. To measure the performance of the implemented hardware, we applied the refining fundamental matrix(RFM), which is a part of 3D reconstruction application. As a result, the implemented system showed similar performance compared to software, and the execution speed increased in a product of 74.3.