• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.76-84
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• 1999

EZW proposed by Shapiro is based on a zerotree constructed in a way that a parent coefficient in a subband is related to four child coefficients in the next finer subband of similar orientation. This fixed treeing based on 1-to-4 parent-child is suitable to exploti hierachical correlations among subbands but not to exploit spatial correlations within a subband. A new treeing by Joo, et al. is suggested to simulatneously exploit those two correlatins by extending parent-child relationship in a flexible way. The flexible treeing leads to increasing the number of symbols and lowering entorpy comparing to the fixed treeing, and therefore a better compression can be resulted. In this paper, we suggest two techniques to suppress the increasing of symbols. First, a probing bit is generated to avoid redundant scan for insignivicant coefficients. Second, since all subbands do not always require the same kind of symbol-set, produced symbols are re-symbolized into binary codes according to a pre-defined procedure. Owing to those techniques, all symbols are generated as binary codes. The binary symbols can be entropy-coded by an adaptive arithmetic coding. Moerover, the binary symbol stream can give comparatively good performances without help of additional entropy coding. Our proposed coding scheme is suggested in two modes: binary coding mode and arithmetic coding mode. We evaluate the effectivenessof our modifications by comparing with the original EZW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.83-89
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• 2006

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

• Journal of Korean Society of Archives and Records Management
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• v.12 no.3
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• pp.29-46
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• 2012

Electronic records are merely series of bits without understanding the formats of content files. There are numerous types of formats and also possibilities of extinction. For long term preservation, it is essential to understand and manage formats. In addition to managing format itself, accurate information on the format needs to be stored for electronic records. In this study, various types of electronic files, without checking with the naked eye, has developed a tool to extract the header information in the format of electronic files with the file extension validation tool to compare format and validate digital component.

• Journal of IKEEE
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• v.24 no.4
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• pp.1184-1187
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• 2020

This paper proposes an in-vehicle network controller fully exploiting the advantages of UART (Universal Asynchronous Receiver/Transmitter) and CAN (Controller Area Network). UART is used in 1-to-1 communication and it exploits parity bit for data integrity check. The proposed in-vehicle network controller converts UART into CAN, which enables multiple communications along with 1-to-1 communication. Also, the proposed in-vehicle network controller exploits CRC (cyclic redundancy check) for data integrity check, which increases communication reliability. CAN is controlled by microprocessor, but the proposed in-vehicle network controller can be controlled by any devices compliant with RS-232, RS-422, and RS-485.

• Proceedings of the Korean Society of Computer Information Conference
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• 2024.01a
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• pp.331-334
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• 2024

하이퍼레저 패브릭(Hyperledger Fabric)은 참여자의 신원을 확인하고, 정보교환(트랜잭션)의 유효성을 검증하는 허가형 블록체인 모델이다. 기존의 대표적인 블록체인 모델인 비트코인, 이더리움과 대비하여 효율적인 데이터 검증 방안이 가능한대, 체인코드와 채널, 그리고 피어를 중심으로 구성되어 있기 때문이다. 먼저 본 블록체인 모델은 '체인코드'라는 스마트 계약(컨트랙트)를 실행하며 허가된 사용자만 네트워크에 참여할 수 있다. 또한, '채널' 기능이 있어 서로 다른 조직 간의 데이터 공유와 검증에 대한 새로운 접근방식을 보여줄 수 있으며, 특정 네트워크 내에서 데이터를 분리할 수 있다. 이를 통해 특정 데이터에 대한 접근권한을 제어하는 기능을 제공하며 동시에 데이터의 신뢰성과 보안성을 높일 수 있다. 마지막으로 '피어'는 체인코드를 통해 들어온 트랜잭션을 검증하고, 유효한 데이터만 원장에 추가하는 기법으로 무결성을 유지하는 데 중요한 역할 담당하고 있다. 본 연구결과를 기반으로 하이퍼레저 패브릭을 효과적으로 활용하여 데이터 검증 프로세스가 산업계에 널리 적용될 수 있기를 기대한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.171-179
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. Encrypt round function and decrypt round function in SPN structure have three parts, round key addition and substitution layer with S-box for confusion and permutation layer for defusion. Most SPN structure for example ARIA and AES uses 8 bit S-Box at substitution layer, which is vulnerable to Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. The symmetric layer is composed with a multiple simple bit slice involution S-Boxes. The bit slice involution S-Box symmetric layer increases difficult to attack cipher by Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. The proposed symmetric SPN block cipher with bit slice involution S-Box is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.249-254
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• 1999

In this paper we analyze the bit error rate of an in-band DAB(Digital Audio Broadcasting) system which is based upon orthogonal frequency division multiplexing(OFDM) and uses M-PSK and M-QAM modulation schemes in the interference environment of an analog FM signal. Results are derived which take into account the influence of the frequency non- selective Rician fading channel, but they are valid for Rayleigh fading channel and AWGN channel as well. Theoretical bit error rates and simulation results are given for system parameters for DAB proposed by ETRI(Electronics and Telecommunications Research Institute).