• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.27-35
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• 2004

Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).

• Journal of the Korean Geotechnical Society
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• v.24 no.8
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• pp.111-123
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• 2008

Geotechnical engineering problems are characterized by many sources of uncertainty. Some of these sources are connected to the uncertainties of soil properties involved in the analysis. In this paper, a numerical procedure for a probabilistic analysis that considers the spatial variability of soil properties is presented to study the response of spatially random soil. The approach integrates a commercial finite difference method and random field theory into the framework of a probabilistic analysis. Two-dimensional non-Gaussian random fields are generated based on a Karhunen-$Lo{\grave{e}}ve$ expansion in a fashion consistent with a specified marginal distribution function and an autocorrelation function. A Monte Carlo simulation is then used to determine the statistical response based on the random fields. A series of analyses were performed to study the effects of uncertainty due to the spatial heterogeneity on the settlement and bearing capacity of a rough strip footing. The simulations provide insight into the application of uncertainty treatment to the geotechnical problem and show the importance of the spatial variability of soil properties with regard to the outcome of a probabilistic assessment.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.4
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• pp.41-46
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• 2004

This paper presents a new semi- systolic architecture for $AB^2$ operation. First of all the previous architecture proposed by Lee et al. is analysed and then we present a new algorithm and it's architecture for $AB^2$ operation based on AOP (all one polynomial) to solve the shortcomings in the architecture. Proposed architecture has an efficient configuration than other previous architectures. It is useful for implementing the exponentiation architecture, which is the core operation in public-key cryptosystems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.761-767
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• 1998

The Perfectly Matched Layer(PML) provide good performance in absorption over a wide frequency range and is an appropriate ABC for waveguides with high dispersion. In this paper, a novel algorithm is proposed to improve the computational efficiency of the PML. In the input and output ports, the fields are decomposed into a series of modes, and then an appropriate ABC is applied to each mode. CPU time and memory storage requirements are greatly reduced, since the computational region is analyzed in one dimension. A WG-90 rectangular waveguide with a thick asymmetric iris is analyzed by Finite-Difference Time-Domain(FDTD) simulations with the conventional PML and the proposed one-dimensional (1-D) PML. Numerical results show that the computational efficiency is significantly improved by the proposed method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.302-305
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• 2001

본 논문에서는 셀룰러 오토마타를 이용하여, GF(2$^{m}$ )상에서 A$B^2$ 연산을 m 클럭 사이클만에 처리할 수 있는 새로운 연산기를 설계하였다. 이는 대부분의 공개키 암호화 시스템에서의 기본 연산인 유한 필드 상의 모듈러 지수(modular exponetiation) 연산기 설계에 효율적으로 이용될 수 있다. 또한 셀룰러 오토마타는 간단하고도 규칙적이며, 모듈화 하기 쉽고 계층화 하기 쉬운 구조이므로 VLSI 구현에도 효율적으로 활용될 수 있다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.605-607
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• 2000

본 논문에서는 유한 필드 GF(2m)상에서 모듈러 곱셈 A(x)B(x) mod p(x)를 수행하는 2-디지트 시리얼 (2-digit-serial) 시스톨릭 어레이 구조인 곱셈기를 제안하였다. LSB-first 곱셈 알고리즘을 분석한 후 2-디지트 시리얼 형태의 자료의존 그래프(data dependency graph, 이하 DG)를 생성하여 시스톨릭 어레이를 설계하였다. 제안한 구조는 정규적이고 서로 반대 방향으로 진행하는 에지들이 없다. 그래서 VLSI 구현에 적합하다. 제안한 2-디지트 시리얼 곱셈기는 비트-패러럴(bit-parallel) 곱셈기 보다는 적은 하드웨어를 사용하며 비트-시리얼(bit-serial) 곱셈기 보다는 빠르다. 본 논문에서 제안한 2-디지트 시리얼 시스톨릭 곱셈기는 기존의 같은 종류의 곱셈기 보다 처리기의 최대 지연 시간이 적다. 그러므로 전체 시스톨릭 곱셈기의 처리시간을 향상시킬 수 있다.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.843-844
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• 2006

자기 기록 시스템이 더 높은 기록 밀도를 가지려면 기록 미디어에 더 작은 공간을 가지는 비트를 기록할 수 있어야 한다. 이를 가능하게 하기 위해서는 더 작은 비트를 보존 할 수 있는 고 보자력 기록 미디어와 이를 기록할 수 있는 자기 기록 헤드가 있어야 한다. 자기 기록 시스템에서 기록 밀도와 함께 중요시 되는 것이 바로 기록 속도이다. 시스템이 발전 할 수록 요구되는 속도 또한 높아지고 있다. 기록 속도가 빨라지려면 기록 주파수가 높아지고 기록 미디어의 회전 속도가 빨라져야 한다. 자기 기록 헤드는 자화되어 있는 고 보자력 기록 미디어 위를 빠른 속도로 직선 운동하고 있는 형태가 되고 이로 인하여 자기 기록 헤드에 와전류가 발생하게 된다. 발생되는 와전류의 형태는 기록 미디어에 자화된 형태에 따라 달라질 것이고 또한 자기 기록 미디어의 회전 속도와 와전류가 발생되는 기록 헤드의 전기전도도에 따라 변화 된다. 본 연구는 이렇게 발생된 와전류를 3차원 유한요소법을 이용하여 분석한 수 이 와전류가 기록 필드에 미치는 영향을 분석하여 제시 하였다.