• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1464-1469
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• 2001

본 논문에서는 디지털 하이브리드 위상고정루프(Digital Hybrid Phase-Locked Loop, DHPLL) 주파수 합성기 구조에서 고 순도 스펙트럼과 초고속 스위칭 속도를 위한 설계기술을 제안한다. D/A 변환기 출력으로 전압제어발진기(Voltage Controlled Oscillator, VCO)를 구동하는 개 루프(open-loop) 구성 방식과 기존 위상고정루프(Phase Locked Loop, PLL)의 폐 루프(closed-loop) 구성 방식을 혼합한 하이브리드 구조의 주파수 합성기를 고려하여, 시스템 변수(개 루프 대역과 위상 여유)와 성능 파라미터(정착시간, 위상 잡음, 그리고 최대 오버슈트(Max. overshoot)의 관계를 연구하였다. 그리고 이 관계를 통해 스펙트럼 순도와 스위칭 속도를 향상시키기 위한 최적의 3가지 설계방안을 제시한다. 컴퓨터 시뮬레이션 결과, 주파수 스위칭 과정에서 발생하는 최대 오버슈트가 0.0991%이고 완전 정상상태 도달시간은 0.288msec이다. offset 주파수 10KHz에서 위상 잡음은 -128.15dBc이다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.205-208
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• 2000

In this paper, we'll show that an improved PDFF controller is obtained by substituting a feedforward compensator in the existing PDFF system with a dual-input describing function, and the controller has the ability of adjusting the bandwidth of a system as well as the phase margin simultaneously. The effectiveness of the proposed controller is confirmed by applying to the DC-motor position control system. As the results of simulation, we know that it is possible to design a controller by which the bandwidth of the closed system and its phase margin are easily adjusted.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.49-56
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• 2002

In this paper, a new controller using non-linear compensator for position control is presented, which we can satisfy the given specifications more easily than the existing one. We suggest an improved PDFE(Integral with Proportional-Derivative-plus-Feedforward) controller by which both phase margin and bandwidth are controlled simultaneously in the controller design problem. Replacing the feed forward term in the PDFF system with a CDIDF(Complex Dual Input Describing Function), the desired phase margin is obtained without diminishing the bandwidth of the closed loop system. The effectiveness of the proposed controller is confirmed through simulations and experiments. As The results of these, we know that it is possible to adjust overall specifications by varying parameters in the improved PDFF system.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.509-510
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• 2016

본 논문은 계통연계형 인버터의 위상추종기법인 SRF-PLL을 모델링하고, FPGA에 구현하기 위해 System Generator를 이용하여 설계하였다. SRF-PLL의 비례-적분 이득은 소신호 해석을 하여 일반화를 통해 입력전압의 크기에 관계없이 적용가능하며, 주파수 응답에서 65도 위상여유를 갖는 안정한 이득을 산정하였다. FPGA 구현을 위해 MATLAB/SIMULINK와 연동 가능한 System Generator를 이용하여 SRF-PLL을 모델링하였으며, MATLAB 기반의 시뮬레이션과 실험을 통하여 위상추종 특성을 분석하였다.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2179-2181
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• 2003

기존의 이산시간 슬라이딩 모드 제어기에서는 주어진 슬라이딩 평면으로부터 등가 제어기를 설계하고 그로부터 폐루프 시스템의 고유값이 결정 되어 폐루프 시스템의 극점을 임의로 배치시키는 것이 어려웠다. 최근 슬라이딩 모드제어에 극점 배치기법을 도입하여 폐루프 시스템의 고유값을 임의로 배치시킬 수 있는 방법이 소개되었다. 그러나 극점 배치 기법은 루프 전달함수의 이득과 위상에 대한 여유도 관점에서 설계된 제어기가 아니므로 직접적으로 이득과 위상에 대한 여유도를 보장하기가 힘들다. 따라서 본 논문에서는 루프 전달함수의 이득과 위상에 대한 여유도를 확보할 수 있고 측정 잡음에 대한 민감성을 줄이기 위해 LTR과 멀티레이트 출력 제어기법을 적용해 해결하는 방법을 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of Aerospace System Engineering
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• v.16 no.1
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• pp.17-27
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• 2022

A certain level of stability margin airworthiness criteria should be met to secure robustness against uncertainties between the real plant and the model in a flight control system design. The U.S. Department of Defense (DoD) specification of MIL-F-9490D and airworthiness certification standard of MIL-HDBK-516B uses gain and phase margin criteria of flight control system. However, the same stability margin criteria is applied at all development phases without considering the design maturity of each development phase of the aircraft. Ultimately, a problem arises when the aircraft operation envelope is excessively restricted. This paper proposes the relation of handling qualities and stability margin, and presents re-established stability margin criteria as a development phases and verification methods. The results of the research study are considered to contribute to the verification of the stability margin criteria more flexibly and effectively by applying the method to not only the currently manned developing aircrafts but also the unmanned vehicle to be developed in the future.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.632-634
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• 2000

The robust design of controllers to ensure gain and phase margin is can be use approximation of arctan function. In this paper, We proposed a tuning algorithm PID controllers based on specified gain and phase margin by a new approximation of arctan function. This method have linear interpolation equations of two arctan interval instead of one arctan interval of arctan(x). It is shown that the frequency response of this method was to ensure specified gain and phase margin.