• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.1
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• pp.7-12
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• 2011

This paper proposes a differential Colpitts-VCO circuit suitable for low phase noise oscillation at the sub-1V supply voltage. Oscillation with low phase noise at the sub-1V supply voltage is facilitated by employing inductors as the current sources of the proposed circuit. One of the two feedback capacitors of the single-ended Colpitts oscillator in the proposed circuit is replaced with the MOS varactor in order to further reduce the resonator loss. Post-layout simulation results using a $0.18{\mu}m$ RF CMOS technology show that the phase noises at the 1MHz offset frequency of the proposed circuit oscillating at the sub-1V supply voltages of 0.6 to 0.9 V are at least 7 dBc/Hz lower than those of the well-known cross-coupled differential VCO.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.202-207
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Korean Journal of Remote Sensing
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• v.34 no.3
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• pp.495-506
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• 2018

Global interest in climate change and sea level rise has led to active research on the velocities of glaciers. In studies about the velocity of glaciers, in-situ measurements can obtain the most accurate data but have limitations to acquire periodical or long-term data. Offset tracking using SAR is actively being used as an alternative of in-situ measurements. Offset tracking has a limitation in that the accuracy of observation is lower than that of other observational techniques, but it has been improved by recent studies. Recent studies in the $Uv{\hat{e}}rsbreen$ glacier area have shown that glacier altitudes decrease at a rate of 1.5 m/year. The glacier displacement velocities in this region are heavily influenced by climate change and can be important in monitoring and forecasting long-term climate change. However, there are few concrete examples of research in this area. In this study, we applied the improved offset tracking method to observe the two-dimensional velocity in the $Uv{\hat{e}}rsbreen$ glacier. As a result, it was confirmed that the glacier moved at a maximum rate of 133.7 m/year. The measruement precisions for azimuth and line-of-sight directions were 5.4 and 3.3 m/year respectively. These results will be utilized to study long-term changes in elevation of glaciers and to study environmental impacts due to climate change.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.638-647
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• 2006

Recently, the DFT-Spread OFDM has been studied for the PAPR reduction. However, the DFT-Spread OFDM produces more ICI and SCI problems than OFDM because phase offset mismatch of the DFT spreading code results from the random phase noise in the oscillator. In this paper, at first, phase noise influence on the DFT-Spread OFDM system is theoretically analyzed in terms of the BER performance. Then, the conventional ICI self-cancellation methods are discussed and two kinds of ICI self-cancellation methods are newly proposed. Lastly, a new DFT-Spread OFDM system which selectively adopts the ICI self-cancellation technique is proposed to resolve the interference problem and PAPR reduction simultaneously. Proposednew DFT-Spread OFDM system can minimize performance degradation caused by phase noise, and still maintain the low PAPR property. Among the studied methods, DFT-Spread OFDM with data-conjugate method or newly proposed symmetric data-conjugate method show the significant performance improvements, compared with the DFT-Spread OFDM without ICI self-cancellation schemes. The data-conjugate method is slightly better than symmetric data-conjugate method.

• Journal of Advanced Navigation Technology
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• v.16 no.6
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• pp.997-1004
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• 2012

In this paper, we propose and implement a signal quality measurement algorithm for CDMA2000 1x terminal. The proposed algorithm is suitable to be implemented in software on a PC-based platform and extract the received signal after carrying out equalization, PN code acquisition and tracking, frequency and phase offset compensation with 4-oversampled input signal. Then, through despreading and demodulation with the extracted signal, the proposed algorithm regenerate the reference signal to be used in measurement. The signal quality is measured using this regenerated signal and the extracted signal.

• Journal of Digital Contents Society
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• v.8 no.3
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• pp.385-391
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• 2007

In this paper, we propose a frequency synchronization algorithm for S-DMT cable modem, which is practicable to the next-generation high capacity upstream physical layer in HFC networks. Analyzing several viable frequency synchronization algorithms of multicarrier systems, we proposed an algorithm using predetermined training sequence of repeated pattern in preamble field and residual frequency offset compensation with pilot signals. We verified that the simulation results of the proposed algorithm in AWGN showed good performance and suitability to the S-DMT upstream cable modem for fast frequency synchronization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.