• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.7-12
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• 2008

In this paper, a highly efficiency power amplifier is presented for multi-band antenna system. The class F power amplifier operating in dual-band designed with one LDMOSFET. An operating frequency of power amplifier is 900 MHz and 2.14 GHz respectively Matching networks and harmonic control circuits of amplifier are designed by using the unit cell of composite right/left-handed(CRLH) transmission line(TL) realized with lumped elements. The CRLH TL can lead to metamaterial transmission line with the dual-band holing capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of all harmonic components for high efficiency is very difficult, we have controled only the second- and third-harmonics to obtain the high efficiency with the CRLH TL. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2719-2730
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• 2009

In this paper, we implement the measurement functionality for performance measurements of EDGE (Enhanced Data Rates for GSM Evolution) terminal by using software. Generally speaking, the receiving algorithms in normal MODEM cannot be used directly to a measurement system due to the lack of accuracy. Therefore, we propose a new receiver algorithm for precise EDGE signal measurements. In the proposed algorithm, 2-stage (coarse stage, fine stage) parameters estimation (symbol-timing, frequency offset, carrier phase) scheme is used. To improve the estimation accuracy, we increase the number of the received signal samples by interpolation. The proposed EDGE signal measurement algorithm can be used for verifying the hardware measurement system, and also can be used for the commercial systems through software optimization.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2369-2378
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• 2009

In this paper, we implement measurement functionality for performance measurement of the GSM (Global System for Mobile Communication) terminal by using software. Generally speaking, the receiving algorithms in normal modems cannot be used directly to the measurement system due to the lack of the algorithm accuracy. In this paper, we propose the new receiver algorithm for precise GSM signal measurements. In the receiving algorithm, 2-stage (coarse stage, fine stage) parameters estimation (symbol-timing, frequency offset, carrier phase) scheme is used. To improve the estimation accuracy, we increase the number of the received signal samples by interpolation. The proposed GSM signal measurement algorithm can be used for verifying the hardware measurement system. In addition, the proposed algorithm can be used for the commercial system through code execution speed optimization.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.107-114
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• 2021

In this paper, a planar transistor oscillator for X-band using a newly proposed L-shaped monopole slot resonator is proposed. For planar design, an L-shaped monopole slot with an open-end is used as a resonator for a transistor oscillator. As a result of the simulated design of the resonator in three stages, a high Q value of 1169.84 and a high insertion loss of 49.934 dB were identified. The results of the final design and manufactured oscillator measurements confirmed that the oscillation output is greater than 7 dBm and has good phase noise characteristics of -58 dBc/Hz at 100 kHz offset. The proposed oscillator is planar and has the advantage of being directly applicable to microwave integrated circuit technology. It also has the advantage of being able to reduce its size as it can only be implemented in microstrip form without additional devices such as metal cavities and tuning screws in 3D structures, as in the case of a DRO (dielectric resonance oscillator).

• The Journal of Korean Institute of Information Technology
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• v.17 no.3
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• pp.43-50
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• 2019

In this paper, we propose a S-band oscillator with a reduced electrical size by applying a vertical split ring resonator(VSRR). The VSRR is a type of split ring resonator that operates as a resonator by the capacitance and inductance generated between the microstrip lines arranged on the top and bottom of the dielectric substrate and it has an advantage that the electrical size of the resonance circuit can be reduced as compared with the conventional ring resonator. In this paper, we design a VSRR operating over S-band and an oscillator using the VSRR as the resonant circuit. The proposed oscillator showed the output of 5.9dBm at 2.4HGz and showed the phase noise characteristics of -112.58dBc at 100KHz offset frequency and -117.85dBc at 1MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.33-40
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• 2005

This paper presents a structure of the searcher using a diversity in array antenna systems operating in the cdma2000 1x signal environments. The new technique exploits the fact that the In-phase and quadrature components of interferers can respectively be viewed as an independent gaussian noise at each antnna element in most practical cdma signal environments. The proposed PN acquisition scheme is a singles-dwell PN acquisition system consisting of two stages, that is, the searching stage and the verification stage. The searching stage independently correlates the receiver multiple signals with PN generator of each antenna element for obtaining the synchronous energy at the entire region. Then, the searching results of each antenna element are non-coherently combinind. The verification stage compares the searching energy with the optimal threshold, which is predesigned in the lock detector, and decides whether the acquisition is successful or fail. In this paper, we analyzed the effect of tile diversity order to determine the mean acquisition time. In general, it is known that the mean acquisition time significantly decrease as the number of antenna elements increases. But, as the diversity order goes up, the enhancement of the performance is saturated. Therefore, to decrease the mean acquisition time of the searcher, we must design the optimal array antenna systems by considering the operating SNR range of the receiver, the probability of detection $P_D$ and that of false alarm $P_{FA}$ . The Performance of the proposed PN acquisition scheme is analyzed in frequency selective Rayleigh fading channels. In this paper, the effect of the number of antenna elements on PN acquisition scheme is shown according to the probability of detection $P_D$ and that of false alarm $P_{FA}$.