• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.134-141
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• 2009

The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.773-778
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• 2007

In order to resolve problems with the phase error in QPSK demodulator of the digital satellite broadcasting systems, the demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the complexity of implementation is reduced by the reduction into half of the number of the multiplier in Inter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table, We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is $175{\mu}W$, NCO with the proposed structure is $24.65{\mu}W$. As the result, it is recognized that about one eight of loss power is reduced. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.71-78
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• 2005

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.522-527
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• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.4
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• pp.309-316
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• 2011

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

• Journal of Satellite, Information and Communications
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• v.7 no.1
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• pp.128-133
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• 2012

In this paper, we analysis the effect of error of code tracking and frequency tracking according to the chip delay of spoofing signal through the simulation. Firstly, we investigate the type of spoofing signal and defense technical of spoofing attack. For simulation, we generated the intermediate spoofing signal using the software GNSS signal generator simulator(SGGS), the intermediate spoofers synchronize its counterfeit GPS signals with the current broadcast GPS signals. The software GPS receiver simulator(SGRS) received the spoofing signal and normal signal from SGGS, and process the signals. In paper, we can check that the DLL and PLL tracking loop error are generated and pseudo-range is changed non-linear according to chip delay of spoofing signal when the spoofing signal is entered. As a result, we can check that navigation solution is incorrectly effected by spoofing signal.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.3
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• pp.60-69
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• 1993

The speed control associated with dc servo motors for direct-drive applications of mobile robot is considered in this study. Robot is moved by power wheeled steering of two dc servo motors mounted to it. In order to cooperate with micro-computer and to achieve the high-performance operation of dc servo motor, speed control system is composed of a digital Phase Locked Loop and H-type drive circuit. And the motor is driven by Pulse Width Modulations. In controlling PWM, it is modified to compose of H-type drive circuit with feedback diodes and switching transistor and design of control sequence so that it may show linear characteristics. As a result, speed characteristics of motor showed linear features. In order to get data on design of PLL control system, the parameters of 80[W[ motor & robot device is measured by simple software control. The PLL speed control system is schemed and designed by leaner drive circuit and measured parameters. A complete speed control system applied to 80[W] dc servo motor showed good linearity, stability and high response. Also, it is verified that the PLL speed control system has good compatibility as a mobile robot driver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.905-913
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• 2006

In the impulse radio ultra-wideband communication systems, the residual timing offset exists when the acquisition and tracking of the timing synchronization is well done. And the offset affects the performance of the system dramatically. In order to compensate the offset, we present the digital phase-locked loop that uses the reference signal in the correlation detection receiver. First, we show the degradation of BER performance that is caused by the offset, and then compensation process of the timing tracker and performance improvement. In this paper, the timing detector in the tracker operates at the sampling period of frame level uses the correlation between received and reference signal. Also, we present the performance comparison by using the computer simulation results for different Gaussian monocycle pulses.