• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1129-1132
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• 2003

본 논문에서는 위상/주파수 검출기을 설계시 문제가 되는 Reference Spur을 없게 하여 Low Noise를 구현할 수 있는 No Spike PFD(Phase Frequency Detector)를 제안한다. 위상동기루프의 특별한 형태로 차지 펌프 위상동기루프가 있다. 차지 펌프위상동기 루프는 일반적으로 3-state 위상/주파수 검출기를 이용한다. 이 3-state 위상/주파수 검출기는 기준 신호와 VCO 출력 신호의 위상차에 비례하는 디지털 파형으로 출력을 내보낸다. 차지 펌프 위상동기루프 그림 1 처럼 디지털 위상/주파수 검출기(PFD), 차지 펌프(CP), 루프 필터(LF), VCO로 구성된다. PFD 는 기준 신호와 VCO 에 의해 만들어진 출력 신호를 입력받아 각각의 위상과 주파수를 비교한다. 즉, 출력 신호가 기준 신호보다 느릴 때에는 출력 신호를 앞으로 당기기 위해서 up 신호를 넘겨주고, 출력 신호가 기준 신호보다 빠를 때에는 출력 신호를 뒤로 밀기 위해 down 신호를 넘겨준다. 차지 펌프(CP)의 전류를 Ip 라고 한다면, CP 에서 LF 로 흐르거나, LF에서 CP로 흐르는 전류 Ip의 평균량이 기준 신호와 VCO 출력 신호의 위상차에 비례하는 것이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.523-524
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• 2016

본 논문에서는 자기저항 (Magnetic Resistive, MR)각도 센서에서 자속 간섭 및 축 진동과 같은 외란에 의해 발생하는 각도맥동을 해결하는 방법이 연구되었다. 외란에 의한 각도 맥동은 일정한 기계각 속도 한 주기 내에서 전기각 속도가 불균일하게 측정되는 현상이다. 이를 해결하기 위해 위상동기루프 (phase locked loop, PLL)를 적용하였고, 자기저항 각도 센서의 각도 맥동을 효과적으로 제거하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.4
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• pp.591-598
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• 2021

The digital phase-locked loops(DPLL) is a circuit used for phase synchronization and has been generally used in various fields such as communication and circuit fields. State estimators are used to design digital phase-locked loops, and infinite impulse response state estimators such as the well-known Kalman filter have been used. In general, the performance of the infinite impulse response state estimator-based digital phase-locked loop is excellent, but a sudden performance degradation may occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a minimum variance finite impulse response filter with optimal horizon for designing a new digital phase-locked loop. A numerical method is introduced to obtain the measured value interval length, which is an important parameter of the proposed finite impulse response filter, and to obtain a gain, the covariance matrix of the error is set as a cost function, and a linear matrix inequality is used to minimize it. In order to verify the superiority and robustness of the proposed digital phase-locked loop, a simulation was performed for comparison and analysis with the existing method in a situation where noise information was inaccurate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.634-640
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• 2000

This paper proposes a new extended decision directed-decision estimated phase recovery algorithm based on maximum likelihood parameter estimation for OQPSK. In this scheme, comparing conventional one, the data dependent noise of phase recovery loop is reduced by inserting filter with 2 taps to in-phase and quadrature-phase channel respectively before phase detector. The proposed scheme is compared to conventionalscheme and OQPSK in aspect to BER(Bit Error Rate) and phase error according to the roll-off factor of baseband filter, the output back-offs of nonlinear satellite channel, and loop bandwidth.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.3
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• pp.106-113
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• 1997

In uninterruptible power supply(UPS), a high speed phase control is usually required to compensate transients in the output voltage at the instant of transfer from the ac line to the inverter when the ac line fails or backs to the ac line in case of the inverter fails. To overcome this problem, this paper pre¬sents the closed digital phase-locked loop(DPLL) techniques designed by full software with TMS320C31 digital signal processor and describes the functional operation of the proposed DPLL. Fi¬nally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.