• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.20.1-20.1
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• 2007

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.232-232
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• 2007

• Proceedings of the Optical Society of Korea Conference
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• 2005.07a
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• pp.50-51
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• 2005

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.89-90
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• 2010

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.263-264
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• 2011

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.102-109
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• 2000

It is difficult to meet the cleanliness requirement of $10^{10}/\textrm{cm}^2$ for the giga level device fabrication with mechanical cleaning techniques like scrubbing which is widely used to remove the particles generated during Chemical Mechanical Polishing (CMP) processes. Therefore, the second cleaning process is needed to remove metallic contaminants which were not completely removed during the mechanical cleaning process. In this paper the experimental results for the removal of the metallic contaminants existing on the wafer surface using remote plasma $H_2$ cleaning and UV/$O_3$ cleaning techniques are reported. In the remote plasma $H_2$ cleaning the efficiency of contaminants removal increases with decreasing the plasma exposure time and increasing the rf-power. Also the optimum process conditions for the removal of K, Fe and Cu impurities which are easily found on the wafer surface after CMP processes are the plasma exposure time of 1min and the rf-power of 100 W. The surface roughness decreased by 30-50 % after remote plasma $H_2$ cleaning. On the other hand, the highest efficiency of K, Fe and Cu impurities removal was achieved for the UV exposure time of 30 sec. The removal mechanism of the metallic contaminants like K, Fe and Cu in the remote plasma $H_2$ and the UV/$O_3$ cleaning processes is as follows: the metal atoms are lifted off by $SiO^*$ when the $SiO^*$is evaporated after the chemical $SiO_2$ formed under the metal atoms reacts with $H^+ \; and\; e^-$ to form $SiO^*$.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.187.2-187.2
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• 2011

태양광산업의 value chain중 up-stream쪽인 고순도 실리콘산업은 셀, 모듈, 시스템 쪽에 비하여 영업 이익률이나 부가가치 측면에서 매우 높은 성장성을 현재 보여주고 있으며 최근 원자력산업의 안전성 문제가 대두됨으로 인하여 태양광수요가 전 세계적으로 증대되는 경향을 나타내어 태양광용 실리콘의 수요가 확대됨과 아울러 spot시장에서의 가격 또한 상승하고 있다. 이런 관점에서 잉곳 및 웨이퍼 가공 중에 발생하는 고순도 실리콘 폐기물의 재활용 이 다시 주목받고 있다. 태양전지 웨이퍼(wafer)용 소재는 6N급 이상의 결정질 실리콘 잉곳(ingot)이 주를 이루며, 고효율의 셀을 제조하기 위해서 단결정 실리콘 잉곳이 많이 사용된다. 실리콘 단결정을 육성하는 방법에는 Floating zone 법, Czochralski 법, Bridgeman 법, CVD 등 매우 다양하다. 이 중 Czochralski 법은 전체 생산량의 대부분을 차지하고 있는 방법으로, 용융액에서 결정을 인상하여 ingot을 제작하는 방법이다. 그러나 대량의 전기에너지를 소비하여 제작되는 고순도의 실리콘 단결정 잉곳은 후 가공공정에서 그 절반 이상이 분말(powder) 및 슬러지(sludge)로 폐기되므로, 자원의 재활용 및 환경오염 측면에서 주요과제가 되고 있다. Czochralski 법으로 제작된 ingot의 경우 그 표면이 매끄럽지 못하여, 웨이퍼 단위의 가공 시 형태가 진원이 될 수 있도록 표면을 미리 연마(grinding)하는데, 이때에도 미세 분말이 다량 발생하게 된다. 본 연구에서는 이러한 고순도 단결정 실리콘 ingot의 연마 가공공정에서 발생한 미세 분말을 용해하여 보았다. 진공 챔버(chamber) 내부에 유도가열 코일과 냉도가니로 구성된 장비를 통해 전자기유도가열을 이용하여 실리콘 분말 폐기물을 용해하고, 그 시편을 ICP-MS 및 비저항 측정을 통해 분말 의 특성을 조사하여 재활용 가능성을 검토해 보았다.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.23-28
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• 2009

We investigated the wafer-level MEMS capping process for which cavity formation in Si wafer was not required. Ni caps were formed by electrodeposition on 4" Si wafer and Ni rims of the Ni caps were bonded to the Cu rims of bottom Si wafer by using epoxy. Then, top Si wafer was debonded from the Ni cap structures by using SnBi layer of low melting temperature. As-evaporated SnBi layer was composed of double layers of Bi and Sn due to the large difference in vapor pressures of Bi and Sn. With keeping the as-evaporated SnBi layer at $150^{\circ}C$ for more than 15 sec, SnBi alloy composed of eutectic phase and Bi-rich $\beta$ phase was formed by interdiffusion of Sn and Bi. Debonding between top Si wafer and Ni cap structures was accomplished by melting of the SnBi layer at $150^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.55-65
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• 1998

In industrial fields, RTP(rapid thermal processing) system is widely used for improving the oxidation and the annealing in semiconductor manufacturing process. The main control factors are temperature control of wafer and uniformity in the wafer. In this paper, we propose an $H^{\infty}$ controller design of RTP system satisfying robust stability and performance using weighted mixed sensitivity miniimization and loop shaping technique. And we need reduction technique because of the difficulty of implementation with the obtained high order controller for original model and reduced models, namely, Hankel, square-root balanced, and Schur balanced methods. An example is proposed to show the validity of the proposed method.