• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.29 no.6
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• pp.667-675
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• 2011

In this paper, we propose an automatic image-to-image registration between high resolution multi-sensor images. To do this, TerraSAR-X image was shifted according to the initial translation differences of the x and y directions between images estimated using Mutual Information method. After that, the Canny edge operator was applied to both images to extract linear features. These features were used to design a cost function that finds matching points based on the similarities of their locations and gradient orientations. For extracting large number of evenly distributed matching points, only one point within each regular grid constructed throughout the image was extracted to the final matching point pair. The model, which combined the piecewise linear function with the global affine transformation, was applied to increase the accuracy of the geometric correction, and the proposed method showed RMSE lower than 5m in all study sites.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.97-108
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• 1994

A modified Karhunen-Loeve transformation technique using normalization and simultaneous diagonalization of two sample covariance matrices is proposed to separate the object from the background. The transformation technique for the separation of local data structure through maximizing the ratio of sample variances between two classes was identified as a promising one for a preprocessing of multi-variate signal processing algorithms using neighborhood operators including morphological filtering. To relate the separation quality of the proposed technique to a morphological measure, average height was defined by using morphological pattern spectrum. A practical implementation of the transformation technique was tested experimentally and the theoretical results were confirmed.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.189-192
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• 2001

In this paper, we desire to design real time image processing system to change a various chromaticity in HDTV that has 1344*806 resolution and requires a high-speed 65MHz operation. In order to change the image chromaticity, it is necessary to calculate the color temperature of the image. Conventional way of calculating the temperature uses 2-D algorithm [1] that requires bulky hardware. This paper propose a one-dimensional color-temperature conversion that reduces the hardware complexity while keeping the performance of the 2-D algorithm. The proposed method is realized by using the Xilinx Virtex FPGA XCV 2000E-6BG560.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2403-2408
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• 2015

For image data the discrete cosine transform (DCT) has comparable energy compaction capability to Karhunen-Loeve transform (KLT) which is optimal. Hence DCT has been widely accepted in various image and video compression standard such as JPEG, MPEG-2, and MPEG-4. Recently some approximate DCT's have been reported, which can be computed much faster than the original DCT because their coefficients are either zero or the power of 2. Although the level of energy compaction is slightly degraded, the approximate DCT's can be utilized in real time implementation of image or visual compression applications. In this paper, an approximate 8-point DCT which contains 17 non-zero power-of-2 coefficients and high energy compaction capability comparable to DCT is proposed. Transform coding experiments with several images show that the proposed transform outperforms the published works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.450-458
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• 2008

In this paper, we propose a real-time stereoscopic display system based on H.264/AVC. We initially acquire stereo-view images from stereo web-cam using OpenCV library. The captured images are converted to YUV 4:2:0 format as a preprocess. The input files are encoded by stereo-encoder, which has a proposed estimation structure, with more than 30 fps. The encoded bitstream are decoded by stereo-decoder reconstructing left and right images. The reconstructed stereo images are postprocessed by stereoscopic image synthesis technique to offer users more realistic images with 3D effect. Experimental results show that the proposed system has better encoding efficiency compared with using a conventional stereo CODEC(coder and decoder) and operates with real-time processing and low complexity suitable for an application with a mobile environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of Digital Convergence
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• v.10 no.9
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• pp.351-356
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• 2012

This paper presents the 2D/3D conversion technique using depth map which is generated based on the haze and relative height cue. In cases that only the conventional haze information is used, errors in image without haze could be generated. To reduce this kind of errors, a new approach is proposed combining the haze information with depth map which is constructed based on the relative height cue. Also the gray scale image from Mean Shift Segmentation is combined with depth map of haze information to sharpen the object's contour lines, upgrading the quality of 3D image. Left and right view images are generated by DIBR(Depth Image Based Rendering) using input image and final depth map. The left and right images are used to generate red-cyan 3D image and the result is verified by measuring PSNR between the depth maps.

• Korean Journal of Remote Sensing
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• v.32 no.6
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• pp.693-701
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• 2016

To make a mosaicked image, we need to estimate the geometric relationship between individual images. For such estimation, we needs tiepoint information. In general, feature-based methods are used to extract tiepoints. However, in the case of textureless images, feature-based methods are hardly applicable. In this paper, we propose a frequency domain matching method for automated mosaicking of textureless images. There are three steps in the proposed method. The first step is to convert color images to grayscale images, remove noise, and extract edges. The second step is to define a Region Of Interest (ROI). The third step is to perform phase correlation between two images and select the point with best correlation as tiepoints. For experiments, we used GOCI image slots and general frame camera images. After the three steps, we produced reliable tiepoints from textureless as well as textured images. We have proved application possibility of the proposed method.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06c
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• pp.533-538
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• 2008

본 논문에서는 GPU의 성능을 이용하여 다시점 거리 영상을 실시간으로 정합하는 3차원 온라인 시스템을 제안한다. 제안한 시스템은 거리영상의 정교한 정합을 위해 IPP 알고리즘을 사용하였으며, 최신 GPU 프로그래밍 기법으로 각광받고 있는 CUDA를 이용하여 정합 알고리즘의 연산비용이 큰 부분에 해당하는 투영과 변환의 반복 부분을 수행하였다. 스테레오 기반 휴대용 거리센서에서 $320{\times}240$ 거리영상을 획득하여 정합 알고리즘을 수행한 결과, 초당 5장의 거리영상을 정합할 수 있었다. 제안한 온라인 시스템은 실시간 3차원 모델 복원 기술이 필요한 로봇위치 인식, 주행용 비전 기술, 문화재 원형 복원 등의 분야에서 활용될 수 있을 것이다.