• Journal of Korea Spatial Information System Society
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• v.6 no.1 s.11
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• pp.73-85
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• 2004

Recently, as the growth of the wireless Internet, PDA and HPC, the focus of research and development related with GIS(Geographic Information System) has been changed to the Real-Time Mobile GIS to service LBS. To offer LBS efficiently, there must be the Real-Time GIS platform that can deal with dynamic status of moving objects and a location index which can deal with the characteristics of location data. Location data can use the same data type(e.g., point) of GIS, but the management of location data is very different. Therefore, in this paper, we studied the Real-Time Mobile GIS using the HBR-tree to manage mass of location data efficiently. The Real-Time Mobile GIS which is developed in this paper consists of the HBR-tree and the Real-Time GIS Platform HBR-tree. we proposed in this paper, is a combined index type of the R-tree and the spatial hash Although location data are updated frequently, update operations are done within the same hash table in the HBR-tree, so it costs less than other tree-based indexes Since the HBR-tree uses the same search mechanism of the R-tree, it is possible to search location data quickly. The Real-Time GIS platform consists of a Real-Time GIS engine that is extended from a main memory database system. a middleware which can transfer spatial, aspatial data to clients and receive location data from clients, and a mobile client which operates on the mobile devices. Especially, this paper described the performance evaluation conducted with practical tests if the HBR-tree and the Real-Time GIS engine respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• Journal of Korean Society of Steel Construction
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• v.10 no.3 s.36
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• pp.473-486
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• 1998

A numerically stable technique to remove the limitation in choosing a shift in the subspace iteration method with shift is presented. A major difficulty of the subspace iteration method with shift is that because of singularity problem, a shift close to an eigenvalue can not be used, resulting in slower convergence. This study solves the above singularity problem using side conditions without sacrifice of convergence. The method is always nonsingular even if a shift is an eigenvalue itself. This is one of the significant characteristics of the proposed method. The nonsingularity is proved analytically. The convergence of the proposed method is at least equal to that of the subspace iteration method with shift, and the operation counts of above two methods are almost the same when a large number of eigenpairs are required. To show the effectiveness of the proposed method, two numerical examples are considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.325-333
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• 2007

An OS requires the device driver to control hardware IPs at application level. Development of a device driver requires specific acknowledge for target hardware and OS. In this paper, we present a system which generates a device driver together with an interface circuit. In the proposed system, an efficient device driver is generated by selecting a basic device driver skeleton, a function module code, and a header file table from the pre-constructed library and an interface circuit is constructed such that the generated device driver operates correctly. The proposed system is evaluated by generating a TFT-LCD device driver on the ARM922T core with 3.5 inch Samsung TFT-LCD in ARM-Linux environment. Experiment result shows that the writing time on the LCD is decreased by 1.12% and the compiled code size is increased by 0.17% compared to the manually generated one. The automatically generated device driver has no performance degradation in the latency of hardware control at the application program level. The system development time can be reduced using the proposed device driver generation system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1753-1759
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• 2009

A weather radar as one of the remote sensing devices to analyze the weather phenomena receives the return echoes which consist of scattered electromagnetic wave signals from rain, cloud and dust particles, etc. These received Doppler weather spectra are analyzed to extract the various characteristic weather information. The mean wind velocity is one of the important weather parameters which can be obtained by a weather radar ed it may be useful in the prevention of weather hazards occurred by the abrupt shift of wind in small geographical scales such as microbursts. It is usually estimated by pulse pair method which is considered to be reliable and very efficient in the computational requirement. However, there are some problems in the accurate estimation of the mean velocity if Doppler spectra of weather signals appear to be asymmetric gaussian or multi-peak spectra. Therefore, in this paper, the problems in the mean estimation of asymmetric Doppler spectra are analyzed and the improved method is suggested.

• JOURNAL OF ELECTRICAL WORLD
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• s.323
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• pp.69-75
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• 2003

불투명한 경제정세의 와중에서도 전기에너지를 지탱하는 근간이 되는 파워 일렉트로닉스 분야는 확실히 그 기술개발을 향상시켜 오고 있다. 특히 파워디바이스는, 지구환경과 생활환경을 보다 쾌적하게 하기 위하여 인버터 장치 등의 각종 전력절약기기와 풍력$\cdot$태양광$\cdot$연료전지 등 클린에너지의 전력제어장치에 없어서는 안되는 반도체디바이스로 성장했다. 파워디바이스 중에서도 IGBT(Insulated Gate Bipolar Transistor)의 기술혁신은 요 20년 사이에 비약적인 성과를 거두었다. 1980년대에 제품화된 IGBT는, 반도체메모리의 초미세가공기술을 도입하면서 $5{\mu}m$에서 서브미크론의 디자인툴로 발전하여, 2000년대에 들어 칩의 전류밀도는 약 2배, 포화전압은 약 $65\%$까지 개량되었다. 이와 같은 IGBT의 변천은, 전력손실을 대폭적으로 저감시켜 에너지절약기기의 전력변환효율 향상에 공헌하고 있다. 파워디바이스의 기술진보에서 또 한 가지 잊지 말아야 할 것은 주변회로의 집적화(集積化)에 의한 고성능$\cdot$고기능화이다. 최근의 인버터용 파워디바이스로 가장 많이 사용되고 있는 파워모듈은, IGBT등의 파워칩과 그 주변회로와의 컬래버레이션에 의한 제품이다. 다시 말하면 구동회로, 전류$\cdot$전압$\cdot$온도센서 및 그것들의 보호회로가 IC(집적회로)에 편입되어 고기능$\cdot$소형화를 촉진시키고 있다. 구동회로는 LVIC (저전압집적회로)에서 HVIC(고전압집적회로)로 발전하여 전류$\cdot$온도 등의 각종 센서도 동일 칩에 설계할 수 있게 되었다. 또 센싱이나 보호기능뿐만이 아니라 출력전류의 제어를 위한 연산기능과 di/dt의 제어기능이 내장되도록 되어 있어 보다. 고성능의 인텔리전트 파워모듈(IPM)이라고 불리우는 새로운 개념의 파워디바이스가 실현되었다. 또한 패키지 기술도 내부배선 인덕턴스의 저감과 트랜스퍼 몰드패키지의 개발로, 소형화뿐만이 아니라 파워칩의 성능$\cdot$기능을 충분히 발휘할 수 있도록 개발이 적극적으로 추진되고 있다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.172-183
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• 1994

In the multidatabase systems(MDBS), local autonomy and global consistency are important issues. Global consistency could be maintained by a global concurrency control algorithm and a global recovery algorithm. In this thesis, we propose a global concurrency control algorithm to ensure local autonomy and to guarantee global serializability, and a global recovery algorithm which is possible to recover the multudatabase from any failures. The proposed global concurrency control algorithm uses bottom-up approach, based on three-level transaction processing model. It can produce a local history that the execution order of subtransactions is identical to their serialization order by using dummy-operations in the server when an indirect conflict is caused between subtransactions due to local transactions. At the global module, it can efficiently validate global serializability of global transactions by checking global serializability only for the global transactions which conflict with each other.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2776-2785
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• 1998

An image retrieval system based on image content is a key issue for building and managing large multimedia database, such as art galleries and museums, trademarks and copyrights, and picture archiving and communication system. Therefore, the interest on the subject of content-based image retrieval has been greatly increased for the last few years. This paper proposes a feature-based image retrieval technique which uses a compound feature vector representing both of color and shape of an image. Color information for the feature vector is obtained using the algebraic moment of each pixel of an image based on the property of regional color distribution. Shape information for the feature vector is obtained using the Improved Moment Invariant(IMI) which reduces the quantity of computation and increases retrieval efficiency. In the preprocessing phase for extracting shape feature, we transform a color image into a gray image. Since we make use of the modified DCT algorithm, it is implemented easily and can extract contour in real time. As an experiment, we have compared our method with previous methods using a database consisting of 150 automobile images, and the results of the experiment have shown that our method has the better performance on retrieval effectiveness.

• Journal of Advanced Navigation Technology
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• v.12 no.4
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• pp.357-365
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• 2008

Broadcast is a efficient interactive method between a server and mobile clients via wireless channel and broadcast environments are incarnating as various applications. Most studies have been proposed in broadcast environments deal with read-only mobile transactions, many applications are emerging recently that need to manage the update transactions at mobile clients. So we propose a concurrency control for mobile transactions consisted mainly of update operations in broadcast environments. As an optimistic approach is applied for scheduling update transactions, repetitive aborts of update transactions are occur due to conflict between transactions. To solve this problem update transactions must have been executed with distributed manner, but unnecessary aborts are occur as well because of continuous restart. Thus, in this paper we propose a method that transactions are executed distributed manner and can avoid unnecessary aborts of update transactions. Proposed method has no unnecessary uplink and can save resources of mobile client.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.662-672
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• 2011

This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.