• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.328-335
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• 2005

bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.1
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• pp.49-57
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• 2005

ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.889-896
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• 2006

ATM Forum has defined a guaranteed frame rate (GFR) service to serve Internet traffic efficiently. The GFR service provides virtual connections (VCs) for minimum cell rate (MCR) guarantees and allows them to fairly share the residual bandwidth. And ATM Forum has recommended a frame-based generic cell rate algorithm (F-GCRA) as a frame classifier, which determines whether an Am cell is eligible to use the guaranteed bandwidth in a frame level. An ATM switch accommodates cells in its buffer or drops them in a frame level according to current buffer occupancy. A FIFO shared buffer has so simple structure as to be feasibly implemented in switches, but has not been able to provide an MCR guarantee for each VC without buffer management based on per-VC accounting. In this paper, we enhance the F-GCRA frame classifier to guarantee an MCR of each VC without buffer management based on per-VC accounting. The enhanced frame classifier considers burstness of TCP traffic caused by congestion control algorithm so as to enable each VC to use its reserved bandwidth sufficiently. In addition, it is able to alleviate the unfairness problem in usage of the residual bandwidth. Simulation results show that the enhanced frame classifier satisfies quality of services (QoSs) of the GFR service for the TCP traffic.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1160-1168
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• 2000

This paper presents a real-time integrated traffic management (RITM) scheme that can effectively manage variable bit rate (VBR) and available bit rate (ABR) traffics having unpredictable characteristics in asynchronous transfer mode (ATM) networks. An unique feature of this scheme is that it has a special ATM cell control block which makes it possible to monitor bursty traffics in real-time so that the delay incurred to measure cell arrival rate is minimized. Additionally, the proposed scheme intends to dynamically reassign the leftover network resources to VBR/ABR connections without any deterioration in quality of service (QoS) of the existing connections. The RITM scheme has been verified to reliably monitor incoming traffics and to efficiently manage network resources by computer simulations. The capability of managing the incoming ATM traffics in real-time helps determine an optimal acceptable number of user connections for a given network condition. We can use this value as a threshold to protect the network from being congested and to find out a cost-effective buffer design method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.73.1-73.1
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• 2010

태양광 시장은 세계적인 금융 위기 속에서도 점점 그 규모가 확대되고 있다. 시장의 규모가 확대되고 있음에도 불구하고 금융 위기를 겪으면서 생산자 중심의 시장에서 수요자 중심의 시장으로 바뀌게 되었다. 이에 따라 더 적은 비용으로 높은 출력의 제품만이 경쟁력을 가지게 됨으로써 효율이 더욱 이슈화되었다. 여러 태양전지 중 가장 점유율이 높은 결정질 태양전지는 일반적인 양산 공정만으로 효율을 높이는데 한계가 있으므로 selective emitter, back contact, light induced plating 등의 새로운 공정을 도입하여 효율을 높이려는 경향이 나타나고 있다. 본 연구에서는, ALD 장치를 사용하여 결정질 태양전지의 후면을 passivation 함으로써 효율을 높이는 방법을 모색하였다. 부동화 층으로는 $Al_2O_3$를 사용하였으며 셀을 제조하여 평가하였다. 실험방법은 p-type의 웨이퍼를 이용하여 습식으로 texturing 후 $POCl_3$ 용액으로 p-n junction을 형성하였고 anti-reflection 막인 SiNx는 PECVD를 사용하여 R.I 2.05, 80nm 두께로 증착하였다. 그런 다음 후면의 n+ layer를 제거하기 위하여 SiNx에 영향을 미치지 않는 용액을 사용하여 후면을 식각하였다. BSF 층은 screen printer로 Al paste를 printing하여 형성하였고 Al etching용액으로 여분의 Al제거한 후 ALD 장치를 이용하여 $Al_2O_3$를 증착하였다. 마지막으로 전극을 형성한 후 laser로 isolation하여 효율을 평가하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.786-793
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• 2004

Autonomous data rate control scheme of current IxEV-DO uplink networks can not supper the various QoS requirements of heterogeneous traffics nor hold rise-over-thermal OtoT) constraints. In this paper, an uplink resource management scheme called the modified weighted g-fair (MWGF) scheduler with RoT filling is proposed and evaluated for heterogeneous traffics in cdma2000 type uplink networks. The proposed scheme belongs to a family of centralized resource management schemes and offers QoS guarantee by using priority metrics as well as lower system loading by holding RoT constraints using RoT filling method. With some case-study simulations, the proposed algorithms shows lower average delays of real time users compared to that of autonomous rate control by 29 - 40 ％. It also shows the 1.0 - 1.3 dB lower received RoT level than autonomous rate control schemes, leading to lower network loading.

• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.83-96
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• 2005

The multichannel switch is an architecture widely used for ATM (Asynchronous Transfer Mode). It is known that the fault tolerant characteristic can be incorporated into the multichannel crossbar switching fabric. For example, if a link belonging to a multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if a fault occurs in a switching element, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithm in multichannel crossbar ATM switches with a view to early fault recovery. The optimal algorithm gives the best performance in terms of time to localization but it is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally more efficient than the optimal one. We evaluate its performance through simulation. The simulation results show that the Performance of the on-line algorithm is only slightly sub-optimal for both random and bursty traffic. There are cases where the proposed on-line algorithm cannot pinpoint down to a single fault. We enumerate those cases and investigate the causes. Finally, a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm The fault recovery algorithm providesadditionalrowsandcolumnstoallowcellstodetourthefaultyelement.