• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1263-1264
• /
• 2007

자계 유도 고상결정화(FESPC)를 이용하여 제작한 다결정실리콘(poly-Si) 박막 트랜지스터(TFT)는 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)보다 뛰어난 전기적 특성과 우수한 안정성을 지닌다. $V_{DS}$ = -0.1 V에서 채널 폭과 길이가 각각 $5\;{\mu}m$, $7\;{\mu}m$인 P형 TFT의 이동도(${\mu}$)와 문턱 전압($V_{TH}$)은 각각 $31.98\;cm^2$/Vs, -6.14 V 이다. FESPC TFT는 일반 poly-Si TFT에 비해 채널 내 결정 경계 숫자가 많아서 상대적으로 열악한 특성을 가진다. 채널 길이 $5\;{\mu}m$인 TFT의 $V_{TH}$는 채널 길이 $18\;{\mu}m$ 소자의 $V_{TH}$보다 1.36V 작지만, 일반적으로 큰 값이다. 이 현상은 채널에 다수의 결정 경계가 존재하고, 수평 전계가 크기 때문이다. 수평 전계가 증가하면, 결정 경계의 전위 장벽 높이가 감소하게 되는데, 이는 DIGBL 효과이다. ${\mu}$의 증가에 따라서, 드레인 전류가 증가하고 $V_{TH}$은 감소한다. 활성화 에너지($E_a$)는 드레인 전압과 결정 경계의 수에 따라 변하는데, 드레인 전압이 크거나 결정 경계의 수가 감소하면 $E_a$는 감소한다. $E_a$가 감소하면 $V_{TH}$가 감소한다. 유리기판 위의 FESPC를 이용한 P형 poly-Si TFT의 $V_{TH}$는 채널의 길이와 $V_{DS}$에 영향을 받는다. 증가한 수평 전계가 결정 경계에서 에너지 장벽을 낮추는 효과를 일으키기 때문이다.

• Journal of the Korean Magnetics Society
• /
• v.16 no.2
• /
• pp.130-135
• /
• 2006

We theoretically demonstrate that the interlayer exchange coupling (IEC) energy can be manipulated by means of an external bias voltage in a $F_1/NM/F_2/S$$(F_1:ferromagnetic,\;NM:nonmagnetic\;metallic,\;F_2:ferromagnetic,\;S:semiconductor\;layers)$ four-layer system. It is well known that the IEC energy between two ferromagnetic layers separated by nanometer thick nonmagnetic layer depends on the spin-dependence of reflectivity to the $F_1/NM/F_2/S$ four-layer system, where the reflectivities at the interface in $NM/F_2$ interface also depends on $F_2/S$ interface due to the multiple reflection of an electron-like optics. Finally, the IEC energy depends on the spin-dependent electron reflectivity not only at the interfaces of $F_1/NM/F_2$, but also at the interface of $F_2/S$. Naturally the Schottky barrier is formed at the interface between metallic ferromagnetic layer and semiconductor, the Schottky barrier height and thickness can be tailored by an external bias voltage, which causes the change of the spin-dependent reflectivity at $F_2/S$ interface. We show that the IEC energy between two ferromagnetic layers can be controlled by an external bias voltage due ti the electron-optics nature using a simple free-electron-like one-dimensional model.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.6
• /
• pp.14-18
• /
• 2019

The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.

• Journal of IKEEE
• /
• v.18 no.4
• /
• pp.447-455
• /
• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

• Journal of the Korean Vacuum Society
• /
• v.15 no.1
• /
• pp.64-72
• /
• 2006

We demonstrated organic light-emitting devices (OLEDs) based on the organic thin-film materials such as tris-(8-hydroxyquinoline) aluminum $(Alq_3)$. The structure of OLEDs was vacuum deposited upon transparent and thin glass substrates pre-coated with a transparent, conducting indium tin oxide thin film. The luminance characteristics, current, capacitance, and dispersion factor for degraded OLEDs, which were made by various bias currents $(0.5mA\;{\leq}\;I_{Bias}\;{\leq}9mA)$, are studied. The current dependences of lifetime were divided at approximately 2mA, and they represented nearly linear behaviors but had different slopes in a logarithmic plot of lifetime versus bias current. With lighting OLEDs, the anomaly of capacitance, as shown in the CV curve, occurred because of two factors, polarization in the bulk of organic materials and the interface between the metal and organic layers. In decayed OLEDs that had lower bias currents of less than 2mA, it was found that the degradation of luminance was related to both the decrease of polarization and to the lowering of the injection barrier.