• Journal of the Korea institute for structural maintenance and inspection
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• v.18 no.4
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• pp.1-9
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• 2014

With the development of quantum computer, the development of the quantum-inspired search method applying the features of quantum mechanics and its application to engineering problems have emerged as one of the most interesting research topics. This algorithm stores information by using quantum-bit superposed basically by zero and one and approaches optional values through the quantum-gate operation. In this process, it can easily keep the balance between the two features of exploration and exploitation, and continually accumulates evolutionary information. This makes it differentiated from the existing search methods and estimated as a new algorithm as well. Thus, this study is to suggest a new minimum weight design technique by applying quantum-inspired search method into structural optimization of planar truss. In its mathematical model for optimum design, cost function is minimum weight and constraint function consists of the displacement and stress. To trace the accumulative process and gathering process of evolutionary information, the examples of 10-bar planar truss and 17-bar planar truss are chosen as the numerical examples, and their results are analyzed. The result of the structural optimized design in the numerical examples shows it has better result in minimum weight design, compared to those of the other existing search methods. It is also observed that more accurate optional values can be acquired as the result by accumulating evolutionary information. Besides, terminal condition is easily caught by representing Quantum-bit in probability.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.29-34
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• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1060-1066
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• 2021

Recently, researches for quantum computers have been carried out in various fields. Quantum computers performs calculations by utilizing various phenomena and characteristics of quantum mechanics such as quantum entanglement and quantum superposition, thus it is a very complex calculation process compared to classical computers used in the past. In order to simulate a quantum computer, many factors and parameters of a quantum computer need to be analyzed, for example, error verification, optimization, and reliability verification. Therefore, it is necessary to visualize circuits that can intuitively simulate the configuration of the quantum computer components. In this paper, we present a novel visualization method for designing complex quantum computer system, and attempt to create a 3D visualization toolkit to deploy large circuits, provide help a new way to design large-scale quantum computing systems that can be built into future computing systems.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.4
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• pp.101-106
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• 2021

Quantum algorithms and quantum computers can break the security of many of the ciphers we currently use. If Grover's algorithm is applied to a symmetric key cipher with n-bit security level, the security level can be lowered to (n/2)-bit. In order to apply Grover's algorithm, it is most important to optimize the target cipher as a quantum circuit because the symmetric key cipher must be implemented as a quantum circuit in the oracle function. Accordingly, researches on implementing AES(Advanced Encryption Standard) or lightweight block ciphers as quantum circuits have been actively conducted in recent years. In this paper, korean lightweight block cipher LEA was optimized and implemented as a quantum circuit. Compared to the previous LEA quantum circuit implementation, quantum gates were used more, but qubits were drastically reduced, and performance evaluation was performed for this tradeoff problem. Finally, we evaluated quantum resources for applying Grover's algorithm to the proposed LEA implementation.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.631-637
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• 2016

Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.5-7
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• 2018

VLSI(Very large scale integration) 기술을 통한 트랜지스터의 소형화를 통해 CMOS 집적 회로의 성능은 지속적으로 발전해 왔다. 이와 같은 기술 발전에 따라 집적 회로를 구성하는 디지털 논리 요소 또한 진화를 하고 있다. 디코더는 부호화된 정보를 다시 부호화되기 전으로 되돌아가는 처리를 하는 디지털 논리 요소이며 컴퓨터 설계에서 많이 사용되는 핵심 요소이다. 본 논문에서는 양자점 셀룰라 오토마타(Quantum Cellular-Automata, QCA)를 사용하여 인에이블 입력을 가진 2-to-4 디코더를 제안하였다. 4-입력 유니버설 게이트의 하나의 입력을 1로 고정시켜 3-입력 NOR 게이트로 사용하며, 입력 값 X와 입력 값 Y의 중복된 배선 수를 감소시키고 한 배선으로 두 게이트에 입력을 연결하여 디코더의 배선 수와 배선 교차부를 최소화한다. 제안안하는 4-to-2 인에이블 디코더는 기존 디코더보다 셀의 개수와 클럭수를 감소시켜 디코더의 성능을 더 효율적으로 향상시켰다. 이를 통해 고속 회로 설계에 활용 및 높은 성능을 기대 할 수 있으며 QCA 연구에 기여할 수 있을 것으로 전망 한다.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.79-88
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• 2020

Quantum computing is regarded as one of the revolutionary computing technologies, and has attracted considerable attention in various fields, such as finance, chemistry, and medicine. One of the promising candidates to realize fault tolerant quantum computing is quantum dot qubits, due to their expectation of high scalability. In this study, we briefly introduce the international tendencies for quantum dot quantum computing. First, the current status of quantum dot gate operations is summarized. In most systems, over 99% of single qubit gate operation is realized, and controlled-not and controlled-phase gates as 2-qubit entangling gates are demonstrated in quantum dots. Second, several approaches to expand the number of qubits are introduced, such as 1D and 2D arrays and long-range interaction. Finally, the current quantum dot systems are evaluated for conducting quantum computing in terms of their number of qubits and gate accuracies. Quantum dot quantum computing is expected to implement scalable quantum computing. In the noisy intermediate-scale quantum era, quantum computing will expand its applications, enabling upcoming questions such as a fault-tolerant quantum computing architecture and error correction scheme to be addressed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.6
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• pp.181-188
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• 2023

Block cipher is not expected to be safe for quantum computer, as Grover's algorithm reduces the security strength by accelerating brute-force attacks on symmetric key ciphers. So it is necessary to check the post-quantum security strength by implementing quantum circuit for the target cipher. In this paper, we propose the optimal quantum circuit implementation result designed as a technique to minimize the use of quantum resources (qubits, quantum gates) for SIMECK lightweight cryptography, and explain the operation of each quantum circuit. The implemented SIMECK quantum circuit is used to check the estimation result of quantum resources and calculate the Grover attack cost. Finally, the post-quantum strength of SIMECK lightweight cryptography is evaluated. As a result of post-quantum security strength evaluation, all SIMECK family cipher failed to reach NIST security strength. Therefore, it is expected that the safety of SIMECK cipher is unclear when large-scale quantum computers appear. About this, it is judged that it would be appropriate to increase the block size, the number of rounds, and the key length to increase the security strength.

• Review of KIISC
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• v.30 no.5
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• pp.111-119
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• 2020

동형암호(homomorphic encryption)는 암호화된 데이터 사이에서 임의의 연산을 가능하게 하는 유망한 암호학적 스킴(scheme)이다. 이를 활용하면 암호화된 데이터를 복호화하지 않고, 암호화된 상태에서 임의의 연산을 수행 할 수 있을 뿐만아니라, 격자를 기반(lattice-based)으로 하여 양자 알고리즘에 내성(resistant)이 있어 안전하다. 하지만, 동형암호를 이해하기 위해서는 전문적인 암호 또는 계산적인 이론의 지식과 이해가 필요하다. 따라서 본 논문에서는 완전동형암호(fully homomorphic encryption)의 기저에 있는 LWE(learning with error) 문제에서부터 완전동형암호의 핵심인 NAND 게이트와 부트스트래핑(bootstrapping)까지의 과정을 어렵지 않게 설명하여 초보자들의 이해를 돕고자 한다.