• Korean Journal of Materials Research
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• v.11 no.3
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• pp.159-163
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• 2001

The success of SDB (silicon wafer direct bonding) technology can be estabilished by bonding on the bonded interface with no defects and Preventing temperature dependent bubbles. In this research, we observed the behavior of the intrinsic bubbles by transmitting the infrared light and the increase of the bubble pressure was found. And, the $SiO_2$-$SiO_2$ bonded wafer was achieved, which generates no intrinsic bubbles in the annealing under the atmospheric pressure. The intrinsic bubbles in the $SiO_2$-$SiO_2$ bonded wafer were generated in the annealing in the ultra high vacuum. This experimental result shows the relation between the bubble growth and the pressure.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.31-38
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• 2015

In order to achieve a high speed and high quality silicon wafer bonding, the room-temperature direct bonding using atmospheric pressure plasma and sprayed water vapor was developed. Effects of different plasma fabrication parameters, such as flow rate of $N_2$ gas, flow rate of CDA (clear dry air), gap between the plasma head and wafer surface, and plasma applied voltage, on plasma activation were investigated using the measurements of the contact angle. Influences of the annealing temperature and the annealing time on bonding strength were also investigated. The bonding strength of the bonded wafers was measured using a crack opening method. The optimized condition for the highest bonding strength was an annealing temperature of $400^{\circ}C$ and an annealing time of 2 hours. For the plasma activation conditions, the highest bonding strength was achieved at the plasma scan speed of 30 mm/sec and the number of plasma treatment of 4 times. After optimization of the plasma activation conditions and annealing conditions, the direct bonding of the silicon wafers was performed. The infrared transmission image and the cross sectional image of bonded interface indicated that there is no void and defects on the bonded wafers. The bonded wafer exhibited a bonding strength of average $2.3J/m^2$.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.45-53
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• 1994

A new type of Si diaphragm was fabricated using Si-wafer direct bonding and two-step electrochemical etch-stopping methods. Using the new diaphragm structure in mechanical sensors, more precise control of cavity depth and diaphragm thickness was achievable. Also, the propagation of the stress, which was generated near the bonding interface, to the surface can be avoided. Finally, a piezoresistive-type Si pressure sensor was fabricated utilizing the diaphragm and a digital pressure gauge, which can display units of pressure, was realized.

• Proceedings of the KAIS Fall Conference
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• 2001.11a
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• pp.169-172
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• 2001

다층 MEMS구조의 기초기판쌍 소재로 쓰일 수 있는 Si∥SiO₂/Si₃N₄∥Si 기판쌍의 직접접합 가능성을 확인하기 위해서 2000Å-SiO₂와 500Å-Si₃N₄층을 가진 직경 10cm의 실리콘 기판을 각각 친수성 및 소수성 표면세척을 하고 청정분위기에서 경면끼리 가접을 실시하였다. 가접된 기판쌍을 통상의 박스형 전기로를 이용하여 400, 600, 800, 1000, 1200℃ 범위에서 2시간 동안 가열하여 접합을 완료하였다. 완성된 기판쌍을 적외선분석기를 이용하여 접합면적을 확인하였고, 면도칼 삽입법으로 접합계면에너지를 측정하였다. 실험온도 범위 내에서 Si∥SiO₂/Si₃N₄∥Si 기판쌍은 1000℃ 이상에서 접합계면에너지는 2,344mJ/㎡을 나타냈으며, 이는 기존의 Si/Si의 동종접합기판쌍과 동등한 수준의 접합강도로서 부가가치가 큰 새로운 조합의 기판쌍 제조가 가능하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.159-159
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• 2003

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2000.05a
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• pp.43-44
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• 2000

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.97-97
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• 2000

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.250-255
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• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.