• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.48-55
• /
• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.41 no.5
• /
• pp.29-36
• /
• 2004

This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.

• Journal of the Korea Society of Computer and Information
• /
• v.6 no.3
• /
• pp.84-90
• /
• 2001

The development of network and the other communication-network can generate serious problems. So, it is highly required to control security of network. These problems related secu be developed and keep up to confront with anti-security part such as hacking, cracking. Th way to preserve security from hacker or cracker without developing new cryptographic algori keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplicator for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplicator enforce the real time processing and prevent outer cracking.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.4
• /
• pp.51-57
• /
• 2003

The development of the communication network and the other network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, we proposed M3 algorithm for the reduced processing time in the montgomery multiplication part. Proposed M3 algorithm using the matrix function M(.) and lookup table perform optionally montgomery multiplication with repeated operation. In this result, modified repeated operation part produce 30% processing rate than existed montgomery multiplicator. The proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2010.11a
• /
• pp.1760-1762
• /
• 2010

본 논문에서 3치가산기와 승산기(multiplier)는 전류모드 CMOS에 의해서 구현된다. 첫째, 3치 T-gate를 집적회로 설계의 유효 가용성을 갖고 있는 전류모드 CMOS를 이용하여 구현한다. 둘째, 3치 T-gates를 이용해 회로가 유한체 GF (3)에 대하여 2변수 3치 가산표 (2-variable ternary addition table) 및 구구표 (multiplication table)가 실현되도록 구현한다. 마지막으로, 이러한 동작 회로들은 1.5 CMOS 표준 기술과 $15{\mu}A$ 단위전류(unit current) 및 3.3V 소스 전압 (VDD voltage)에 의해 활성화 된다. 활성화 결과는 만족할 만한 전류 특성을 나타냈다. 전류 모드 CMOS에 의하여 실행되는 3치가산기 및 승산기는 단순하며 와이어 라우팅(wire routing)에 대하여 정규적이고, 또한 셀 배열 (cell array)과 함께 모듈성 (modularity)의 특성을 갖고 있다.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1994.06a
• /
• pp.409-412
• /
• 1994

• The Magazine of the IEIE
• /
• v.28 no.4
• /
• pp.103-104
• /
• 2001

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.4A
• /
• pp.447-457
• /
• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.10C
• /
• pp.1008-1014
• /
• 2002

This paper is concerned about multiplierless interpolation FIR filters. In this paper, we propose a filter that performs T tap 1:N interpolation FIR filter operation with B-bit inputs without using multipliers. This is done by applying a method which converts a 2s complement multi-bits input to multiple single-bit inputs and a lookup table minimization method which reduces the size of lookup tables by use of the symmetry of filter coefficients and the symmetry of each lookup table. Two FIR filters are implemented using the methods proposed in this paper. Each of the two filters respectively follows the two design parameters in the specification of IMT-2000. Those two FIR filters have an advantage that the number of required gates is reduced up to 70% comparing to that of a conventional transversal FIR filter.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.14 no.3
• /
• pp.41-48
• /
• 2004

Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.