• 유체기계공업학회:학술대회논문집
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• 2003.12a
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• pp.639-645
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• 2003

Design optimization of a transonic compressor rotor (NASA rotor 37) using response surface method and three-dimensional Navier-Stokes analysis has been carried out in this work. Baldwin-Lomax turbulence model was used in the flow analysis. Two design variables were selected to optimize the stacking line of the blade, and mass flow was used as a design variable, as well, to obtain new design point at peak efficiency. Data points for response evaluations were selected by D-optimal design, and linear programming method was used for the optimization on the response surface. As a main result of the optimization, adiabatic efficiency was successfully improved, and new design mass flow that is appropriate to an improved blade was obtained. Also, it is found that the design process provides reliable design of a turbomachinery blade with reasonable computing time.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1023-1024
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• 2007

외전형 모터는 내전형 모터에 비해 회전하는 회전자 부분이 외부에 존해해서 적은 토크에도 많은 출력을 얻을 수 있고 크기도 줄일 수 있기 때문에 송풍기용으로 많이 사용되고 있고, 점차적으로 프리미엄화 되어가고 있기 때문에 BLDC 모터를 채용하고 있는 추세이다. 본 논문에서는 기존에 양산되는 송풍기용 BLDC 모터를 대상으로 원가를 증가시키지 않고 출력 특성을 향상시키기 위한 최적 사양의 설계를 위해 다양한 변수들을 가지고 해석을 수행하였다. 또한 출력특성을 개선하기 위해서 코일의 선경, 턴 수와 적층 길이, 스큐 각도와의 상관 관계를 해석하여 외전형 BLDC 모터의 성능을 분석하여 보았고 모터의 전체적인 성능 향상과 원가 절감 등의 관점에서 해석을 수행하였다.

• Journal of the Society of Naval Architects of Korea
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• v.31 no.3
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• pp.112-118
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• 1994

In this paper, statistical approach to prediction of A-weighted noise level in ship cabins. based on multiple linear regression analysis, is conducted. The best regression formula is composed of seven parameters of the deadweight, the type of ship, the location of engines and cabins, the type of deckhouse and the propeller skew angle. Verification work was carried out with other 210 cabins' data in 6 ships. As a result, the formula ensures the accuracy of 3 dB(A) in 77 % of cases.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.17-26
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• 1999

In this paper, Bit selectable and Bi-directional Interface Device is described, which can communicate data with the peripheral devices. Specially, an algorithm of truth-table comparison that synthesizes the pulse-type sequential circuit pulse has been proposed to design the Interrupt Generator, and implemented in designing the Interrupt Register. Also, a description of the asynchronous design method is given to remove the clock skew phenomenon, and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.7ns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Journal of KIISE:Information Networking
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• v.27 no.2
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• pp.123-130
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• 2000

It is important interest for us to solve skew problem in intermedia synchronization and to solve jitter problem in intramedia synchronization. It propose multimedia synchronization model to represent mixed media which contain temporal media and spatial media, and that helps us to develop multimedia application software efficiently. The proposed paper use four parameters to deal with QoS of intermedia synchronization and relative duration time algorithm and jitter-compensatory time algorithm are presented. When key medium is destroyed we make a delay as much as maximum delay jitter of the key medium in order to playout the other medium as much as that. The result is that the application of maximum delay jitter improves the service quality.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.75-80
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• 1999

Multimedia synchronization model for distributed, continuous or discrete media that was guaranteed high quality of service is requited in developing multimedia application software. In this paper we have specific object controller which is called dynamic key media that is changed by user event generation. This becomes media whose event occurrence and periods can't be predicted. For event occurrence not only audio but also text and image can be chosen for key media and performs its role. Object controller transfers information for next transition. The proposed model offers high qualify of services by permitting maximum allowed jitter and skew in playout time and verified its effectiveness by simulation.