• Journal of Energy Engineering
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• v.9 no.4
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• pp.309-318
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• 2000

핀-관 열교환기의 효율을 증대시키기 위하여는 열저항을 결정하는 데 있어서 중요한 역할을 하는 공기측 열전달 특성의 향상이 필요하다. 본 연구에서는 핀-관 열교환기의 공리측 성능을 해석하기 위해서 3차원 비압축성 Navier-Stokes 코드를 개발하였으며 이 코드는 시간항에 스칼라 내재적 근사분해법(scalar implicit approximate factorization)절차, 공간항에 유한체적법과 2차의 풍상차분법(upwind differencing)을 사용한다. 서로 다른 3개의 핀형상(평판핀, 슬릿핀, 파형핀)을 고려하였고 이들의 유동 및 열전달 특성을 연구하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1217-1220
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• 2005

In this paper, statistical simulation is applied to a superscalar digital signal processor architecture using DSP kernel and DSP application benchmarks. As a result, the performance of a digital signal processor with several microarchitecture configurations can be estimated with the relative error of 3.7 ${\backslash}%$ on the average.

• Journal of the Korean Society for Precision Engineering
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• v.8 no.4
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• pp.76-83
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• 1991

자기회귀-이동평균모델에 의하여 시스템의 파라미터를 추정할 수 있는 벡터채널 원형 격자 필터(vector channel circular lattice filter)의 알고리즘을 제시하였다. 이 알고리즘은 스칼라 연산만으로 이루어져 계산이 간단한 장점이 있다. 3자유도 시스템의 시뮬레이션 결과로부터 격자 필터의 성능을 검증하였으며, 1자유도 팔의 고유진동수와 감쇄비를 추정하였다.

• Annual Conference of KIPS
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• 2005.05a
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• pp.1653-1656
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• 2005

볼륨 렌더링은 스칼라 데이터로 구성된 3 차원 볼륨 데이터를 가시화하는 기법을 가리키며, 유체 역학, 지진, 기상, 해안, 천문, 의료 등 다양한 분야에서 데이터를 분석하는데 널리 사용된다. 최근에는 대용량 볼륨 데이터가 생성되면서 고해상도 디스플레이에 대한 요구가 높아졌으며, 이에 따라 타일형 디스플레이 장치에서 볼륨 데이터를 가시화하려는 시도가 많이 이뤄지고 있다. 본 논문에서는 타일형 디스플레이 장치에서 볼륨 데이터를 가시화하는 기법을 구현했다. 볼륨 데이터 렌더링은 타일형 디스플레이 장치와 연결된 PC-클러스터에서 그래픽스 하드웨어를 사용하는 볼륨 렌더링 기법으로 수행했으며, 이렇게 렌더링된 결과 이미지를 컴포지팅함으로써 해당 디스플레이 장치에 적절한 이미지를 생성했다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.10 no.2
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• pp.71-77
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• 1996

The end-ring may contribute a significant influence to the performance of machine. The induced currents flow through the bars of a cage rotor and complete their closed paths by passing around the end-ring. This dissertation is to describe a method for calculating end-ring resistance of squirrel cage rotor, based on 3-D finite element method(A-$\Phi$). The resistance under consideration of skin effect is calculated by using Joule's loss equation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.