• Proceedings of the Korean Society for Rock Mechanics Conference
• /
• 2008.03a
• /
• pp.79-88
• /
• 2008

Since the hydraulic fracturing field testing method was introduced first to Korean geotechnical engineers in 1994, there have been lots of progresses in a hardware system as well as an interpretation tool. The hydrofracturing system of first generation was the pipe-line type, so it was not easy to handle. It had been modified to a wire-line system at their second generation. It was more compact one but it also needed an additional air-compressor. Our current system is much more compact and operated by all-in-one system, so it doesn't need an additional air-compressor. With a progress in a hardware system, the software for analyzing the in-situ stress regime has also been progressed. For example, the shut-in pressure, which is the most ambiguous parameter to be obtained from hydrofracturing pressure curves, can now be acquired automatically from the various methods. While the hardware and software for hydrofracturing tests are being developed during the last decade, the author could accumulate the field test results which can cover the almost whole area of South Korea. Currently these field data are used widely in a feasibility study or a preliminary design step for tunnel construction in Korea. Regarding the difficulties in a site selection and a test performance for the in-situ stress measurement at an off-shore area, the in-situ stress regime obtained from the field experiences in the land area can be used indirectly for the design of a sub-sea tunnel. From the hydrofracturing stress measurements, the trend of magnitude and direction of in-situ stress field was shown identically with the geological information in Korea.

• Journal of the Korean Society of Radiology
• /
• v.15 no.4
• /
• pp.507-518
• /
• 2021

Magnetic resonance imaging (MRI) is a key technology that has been seeing increasing use in studying the structural and functional innerworkings of the brain. Analyzing the variability of brain connectome through tractography analysis has been used to increase our understanding of disease pathology in humans. However, there lacks standardization of analysis methods for small animals such as mice, and lacks scientific consensus in regard to accurate preprocessing strategies and atlas-based neuroinformatics for images. In addition, it is difficult to acquire high resolution images for mice due to how significantly smaller a mouse brain is compared to that of humans. In this study, we present an Allen Mouse Brain Atlas-based image data analysis pipeline for structural connectivity analysis involving structural region segmentation using mouse brain structural images and diffusion tensor images. Each analysis method enabled the analysis of mouse brain image data using reliable software that has already been verified with human and mouse image data. In addition, the pipeline presented in this study is optimized for users to efficiently process data by organizing functions necessary for mouse tractography among complex analysis processes and various functions.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.40 no.4
• /
• pp.214-221
• /
• 2003

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.7
• /
• pp.970-979
• /
• 1993

In this paper, a multi-function processor unit is implemented for binary image processing. This unit consists of a set of address generatior, window pipeline register, look up table, control unit, and two local memories .The merits of multi-function processor unit are more simpler than basic SAP and improved disposal speed. A simple software selection give the various choices of image sizes and it can process the function of smoothing, thinning, feature extraction, and edge detection, selectively or sequentially.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.263-272
• /
• 2005

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

• The Journal of the Korea Contents Association
• /
• v.11 no.6
• /
• pp.135-143
• /
• 2011

Visual effect production by computer graphics techniques has become more important in these days. However, there are three problems in the domestic contents production environments. First of all, most Korean film companies have insufficient generally potential to maintain and support their R&D (Research and Development) teams. Secondly, they are much dependent on the abroad commercial software tools. Finally, many people have to participate in the image production pipeline, called the labor-intensive pipeline. In producing a demonstration work, "The Sixty -miles-an-hour man", we have evaluated the usefulness of the developed camera tracking and image composition methods and then examined various production consideration elements. In addition, in order to develop a productive technical element and write a competitive film script, mutual understanding between the developers and the production users should be achieved. Also, this paper describes a role of the technical supervisor to direct the production environment in detail.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.3
• /
• pp.21-29
• /
• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
• /
• 2007.11a
• /
• pp.288-293
• /
• 2007

미국 911 테러 발생 이후로, 국가 기반시설(예: 송/배전 전력망, 석유/가스 파이프라인, 원자력 발전소, 정보통신 시설, 교통 시설, 금융 시설, 매스미디어 시설 등)에 대한 테러리스트의 사보타지 리스크를 관리하는 도전문제에 정부 차원이나, 기업 차원에서 국내외적으로 뜨거운 이목이 집중되고 있다. 그 가운데 에너지 시스템, 특히 원자력 발전소의 물리적 보안은 국가 안보 차원에서 매우 중대한 이슈가 되고 있다. 이는 사보타지로 인한 이러한 시스템의 파손이 국민, 작업자, 또는 외부 환경에 방사성물질 누출과 같은 중대한 결말을 초래할 수 있기 때문이다. 원전과 같은 복잡 시스템에서 설계 기준 위협이 초래할 수 있는 이러한 결말은 그 시스템의 특정 핵심 표적(예: 부품, 구역, 자산, 행위, 인원)의 방호를 통해 효과적으로 방어될 수 있다. 다시 말하면, 표적 인식에서는 어떻게 방어할 것인가에 앞서서 무엇을 방어할 것인가를 다루려는 것이다. 이 연구의 주요 목적은 여태까지 개발된 다양한 표적 인식 기법의 개발 추세를 소개하고 향후 전망을 제시하는 데에 있다. 이를 통해 표적 인식 기법의 수월성, 신뢰성, 및 경제성을 제고할 수 있으리라 본다. 표적 인식 기술의 활용성 측면에서 볼 때, 표적 인식은 하드웨어 적이거나 소프트웨어적인 방호 시스템의 설계에 필수적이므로, 신뢰성 높은 표적 인식은 다음과 같은 긍정적인 파급 효과를 줄일 수 있다: 1) 사보타지 리스크 감소에 직간접적으로 기여할 수 있다; 2) 제한적인 보안 재원을 효율적으로 할당할 수 있다; 3) 보안 대응군대의 훈련 시나리오를 개발할 수 있다; 4) 발전소 규제요건인 안전조치 계획을 비용이나 보안 측면에서 향상시켜 국민 안심(public easiness)을 도모할 수 있다. 향후에는 보다 더 광의적인 복잡 시스템 사이에서 상호 연계적인 사보타지에 대한 표적 인식의 기법들이 점검될 필요성이 있다고 본다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.281-284
• /
• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.45 no.1
• /
• pp.1-10
• /
• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.