Journal of the Institute of Electronics Engineers of Korea CI (전자공학회논문지CI)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Multi-standard Video Codec on Embedded System

임베디드 시스템에서의 다중 표준 영상 코덱

  • Kim, Ki-Chul (Department of Electrical & Computer Engineering, University of Seoul) ;
  • Kim, Min (Department of Electrical & Computer Engineering, University of Seoul)
  • 김기철 (서울시립대학교 전자전기컴퓨터공학부) ;
  • 김민 (서울시립대학교 전자전기컴퓨터공학부)
  • Published : 2003.07.01
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Abstract

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

본 논문에서는 H.261과 H.263 표준을 모두 만족하는 영상 코텍을 임베디드 시스템에서 구현한다. 효율적인 실시간 처리를 위하여, 영상 코덱은 하드웨어 모듈과 소프트웨어 모듈로 구분되어 임베디드 시스템에서 통합 설계된다. 소프트웨어 모듈은 실시간 운영체제와 RISC 프로세서를 이용하여 수행되며, 하드웨어 모듈과 연동하여 실시간으로 영상을 압축하고 복원한다. 시스템 버스로는 AMBA AHB가 사용되며 하드웨어 모듈은 AMBA AHB의 마스터(master)와 슬레이브(slave)의 역할을 모두 수행한다. 영상 압축과정을 실시간으로 처리하기 위하여 인코더의 하드웨어 모듈은 파이프라인으로 설계된다. 구현된 영상 코덱은 H.261과 H.263 표준에 준하여 33㎒의 동작 주파수에서 1초 동안에 CIF 화면 15장을 동시에 압축하고 복원한다.

Keywords

References

  1. ITU-T, 'Video coding for low bit-rate communication,' H.324, February 1998.
  2. 3GPP Technical Specification 3G TS 26.111 V5.0.0.,Modifications to H.324,' 2002.6.
  3. ITU-T, 'Video CODEC for audio-visual services at p x 64kbit/s,' ITU-T Recommendation H.261, 1993.
  4. ITU-T, 'Video coding for low bit-rate communication,' Draft Recommendation H.263, 2 May 1996.
  5. H. Fujiwara, M. L. Liou, M.-T. Sun, K. M.Yang, M. Maruyarma, K. Shomura, and K. Ohyama, 'An all-ASIC implementation of a low bit-rate video codec,' IEEE Trans Circuits systems Video Technol., vol. 2, no. 2, pp. 123-134, June 1992. https://doi.org/10.1109/76.143412
  6. M. Harrand, M. Henry, p. Chaisemartin, P. Mougeat, Y. Durand, A. Tournier, R. Wilson, J.-C. Heruison, J.-C Kongchambon, J.L. Bauer, M. Runtz, and J. Bulone, 'A single-chip videophone video encoder/decoder,' in Proc. ISSCC95, pp. 292-293. https://doi.org/10.1109/ISSCC.1995.535561
  7. M. H. Miki, G.Fujita, T.Onoye, I. Shirakawa, 'Low-Power H.263 Video Codec Dedicated to Mobile Computing,' Proceedings., pp. 80-83, 1997. https://doi.org/10.1145/263272.263288
  8. W. S. Chen, Y. Y. Peng, Y.T. Chang, J.T.Wang, 'Design and implementation of real-time software-based H.261 video codec,' Consumer Electronics, 2001. ICCE. International Conference, 2001. https://doi.org/10.1109/ICCE.2001.935302
  9. H. Igura, S. Narita, Y. Naito, K. Naito, K. Kazama, I. Kuroda, M. Motomura, and M. Yamashima, 'An 800MOPS 110mW 1.5V parallel DSP for mobile multimedia processing,' in Proc. ISSCC98, pp. 293-293. https://doi.org/10.1109/ISSCC.1998.672471
  10. M. Harrand, et al., 'A Single-Chip CIF 30Hz H.261, H.263 and H.263+ Video Encoder/Decoder with Embedded Diplay Controller,' ISSCC Digest of Technical Papers, 1999, pp. 268-269. https://doi.org/10.1109/ISSCC.1999.759240
  11. 김명진, 이상희, 김근배, ' 모듈하된 구조에 기반한 H.263 비디오 코텍 VLSI의 설계,' 전자공학회 논문지, 제39권 SP편 제 5호, 2002년 9월, pp. 477-485
  12. K. R. RAO, J.J. HWANG, 'Techniques & Standards For Image Video & Audio Coding,' Prentice Hall, 1996.
  13. M. N. Pettigrew and V. K.Madisetti, 'Progresses in algorithms and VSLI architecture for motion estimation and compensation in video compression,' Technical Report, Center for Signal and Image Processing, Geogia Institute of Technology, 1995.
  14. K. M.Yang, M. T. Sun, L. Wu, 'A Family of VLSI design for the Motion Compensation Block Matching Algorithm,' IEEE Trans. on circuits and systems for Video Tech., Vol. 36, No. 10, pp. 1317-1325, Oct. 1989. https://doi.org/10.1109/31.44348
  15. Technical Report, Center for Signal and Image Processing Progresses in algorithms and VSLI architecture for motion estimation and compensation in video compression M.N.Pettigrew;V.K.Madisetti
  16. IEEE Trans. on circuits and systems for Video Tech v.36 no.10 A Family of VLSI design for the Motion Compensation Block Matching Algorithm K.M.Yang;M.T.Sun;L.Wu https://doi.org/10.1109/31.44348