• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.1
• /
• pp.47-52
• /
• 2004

This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2016.07a
• /
• pp.13-15
• /
• 2016

에너지 소비가 큰 건물은 내부 온/습도, 이산화탄소 농도, 미세먼지 농도 등의 일정 공기 질을 유지하면서 에너지 비용을 최소화할 수 있는 제어계획을 수립하는 것이 필요하다. 기존 건물에서 실내 환경의 운영은 설정된 실내 환경 값을 기준을 벗어나면 설비 기기를 제어하는 방식으로 이루어진다. 이는 단 시간에 고에너지를 투입하여 장비를 가동시키므로 에너지 소모가 크며 peak 전력이 높아 에너지 비용이 크다는 문제가 있다. 따라서 온도를 포함한 환경이 변해가는 상황을 예측하고 사전에 에너지 사용 계획을 수립하여 관리 제어를 수행함으로써 예열부하 등의 불필요한 에너지 손실을 절감하려 한다. 이를 위해 실내 환경이 변화하는 것을 예측하고 후보 제어계획으로 제어를 수행할 때 소요되는 에너지가 어느 정도인지 시뮬레이션하여 제어계획의 적합도를 평가한다. 기존 EnergyPlus와 같은 시뮬레이션 도구는 모델이 복잡하여 시뮬레이션에 많은 시간이 필요하기 때문에 환경 변화를 반영하기 위해 주기적으로 재수립되는 수많은 제어계획 데이터를 단시간에 시뮬레이션하기에 부적합하다. 본 논문에서는 빠른 시뮬레이션을 위해 실제 운영 데이터와 에뮬레이션을 통해 획득한 운영 데이터를 기반으로 학습 알고리즘을 이용하여 제어계획 적용 시의 미래 상황을 예측한다.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2718-2721
• /
• 2011

This research developed a remote communication system for automatic water meter reading and charge calculation from the field of a house or apartment complexes within the same district. Developed system was applied to perform measurements of the pulse-sensing technology, the minimum power consumption, temperature compensation, short-range wireless communications technology, the handset and wireless communication capabilities of the DB management embedded software to efficiently control. Through this reading-related tasks that are required in a temporal, material and human resources can be minimized.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.3
• /
• pp.161-171
• /
• 2010

As embedded systems adopt monolithic kernels, NAND flash memory is used for swap space of virtual memory systems. While flash memory has the advantages of low-power consumption, shock-resistance and non-volatility, it requires garbage collections due to its erase-before-write characteristic. The efficiency of garbage collection scheme largely affects the performance of flash memory. This paper proposes a novel garbage collection technique which exploits data redundancy between the main memory and flash memory in flash memory-based virtual memory systems. The proposed scheme takes the locality of data into consideration to minimize the garbage collection overhead. Experimental results demonstrate that the proposed garbage collection scheme improves performance by 37% on average compared to previous schemes.

• The KIPS Transactions:PartA
• /
• v.12A no.7 s.97
• /
• pp.571-582
• /
• 2005

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that dose not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read and write operations is a page. A NAND flash file system called YAFFS has been proposed. But YAFFS has several problems to be addressed. In this paper, the Reliable Flash File System(RFFS) for NAND flash memory is designed and evaluated. In designing a file system the following four issues must be considered in particular for the design: (i) to minimize a repairing time when the system fault occurs, (ii) to balance the number of block erase operations by offering wear leveling policy, and (iii) to reduce turnaround time of memory operations by reducing the amount of data written. We demonstrate and evaluate the performance of the proposed schemes.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.21 no.4
• /
• pp.436-441
• /
• 2011

A TPMS is a wireless communication system designed to monitor its condition inside the pneumatic tires on various types of vehicles. These systems report the tire pressure information to the driver of the vehicle. While wireless communications is used to transmit the measurement data from TPMS sensors to a central processing unit in the vehicle, it suffers from the various interferences such as sensors of each tire or outside electrical equipments. Based on the conventional beamformer, a switching beamforming technique is proposed to minimize the interference and efficiently receive valid data. Moreover, in order to minimize the interference and reduce power consumption for communication, a system with unique Gold Code is presented for each tire. The performance of interference suppression is illustrated by computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.56-63
• /
• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.3
• /
• pp.487-494
• /
• 2020

In this paper, we propose a current memory circuit design that reduces static power consumption and maximizes the advantages of current mode signal processing. The proposed current memory circuit minimizes the problem in which the current transfer error increases as the data transfer time increases due to clock-feedthrough and charge-injection of the existing current memory circuit. The proposed circuit is designed to insert a support MOS capacitor that maximizes the Miller effect in the current transfer structure capable of low-power operation. As a result, it shows the improved current transfer error according to the memory time. From the experimental results of the chip, manufactured with MagnaChip / SK Hynix 0.35 process, it was verified that the current transfer error, according to the memory time, reduced to 5% or less.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.213-216
• /
• 2007

The paper deals with a approach to underwater acoustic based Ad-hoc communication, which allows major design strategies for Media Access Control (MAC) within a group of the autonomous underwater vehicles(AUV). The proposed MAC aims at deploying AUV-centric star topology, which minimizes overhead of sensor nodes and improves energy-efficiency. Furthermore, that is also well under long and unknown propagation delays of the underwater acoustic medium. The implemented MAC protocol makes it easier to achieve frame synchronization than TDMA due to deploying localized schedule time, in addition to saving energy consumption by letting nodes sleep. It is also superior to MACA and MACAW in terms of propagation delay. This scalable centralized protocol has the potential to serve as a primer for development of MAC protocol for future underwater acoustic based ad-hoc networks.

• Journal of Biomedical Engineering Research
• /
• v.18 no.4
• /
• pp.467-476
• /
• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.