• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.215-220
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• 2002

In this paper, the 100 watt unit ower amplifier using temperature independent biasing for DTV (Digital Television) repeater application is designed and fabricated. The DC operation point of this unit power amplifier at temperature variation from $20^{\circ}C$ to $100^{\circ}C$ is fixed by active bias circuit. The variation of current consumption in the 100 watt unit power amplifier has an excellent characteristics of less than 0.6A. The implemented unit power amplifier has the gain over 12dB, the gain flatness of less than 0.5dB and input and output return, loss of than 15dB over the DTV repeater frequency range (470~806MHz). This unit power amplifier yields intermodulation distortion(IMD) of more than 32dBc at 2MHz offset, which satisfies the IMD at output power of 100 watt (50dBm).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.29 no.4
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• pp.366-375
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• 1984

In order to confirm the effect of climatic consumption index (C C I) on the number of spikelets and yield of rice, 3 levels of shading rates such as 0, 25, 50% of full light were treated during the tillering stage, reproductive growth stage and ripening period, respectively, in a phytotron controlled with day/ night temperature of 20/10$^{\circ}C$ and 30/20$^{\circ}C$, and field at Crop Experiment Station, Suwon, Korea. The results are as follows: 1. As solar radiation decreased during the reproductive growth stage in 30/20$^{\circ}C$ or field condition, the number of spikelets per panicle was decreased due to the decrease of the number of differentiated secondary rachis branches and spikelets as well as the increase of the number of degenerated secondary rachis branches and spikelets. 2. Our results showed slight negative correlation between C C I of the reproductive growth stage and number of panicles per square meter and number of differentiated secondary rachis branches. On the other hand, there was highly significant positive correlation between C C I of the reproductive growth stage and the number of degenerated secondary rachis branches and spikelets, and negative correlation in number of differentiated spikelets. 3. The shading during the reproductive growth stage did not affect on the percentage of ripened grains and 1000 grains weight of hulled rice, whereas those were decreased with shading during the ripened period. 4. Influence of shading in each growing stage on the yield was severe in the order of ripened period, reproductive growth stage, tillering stage. 5. Respiration rate in Jinheung was higher than that of Tongil at low temperature, but reversed above 30$^{\circ}C$. Respiratory coefficients (Q$\sub$10/) of Tongil and Jinheung were 2.74 and 1.96, respectively. Respiration/ photosynthesis ratio in Jinheung was higher than that of Tongil at low temperature, while higher in Tongil above 32$^{\circ}C$. 6. Transportation of $\^$14/C was restricted at 20/10$^{\circ}C$ in Tongil, however, there was no differences at 30/20$^{\circ}C$ in both Tongil and Jinheung. The influence of shading on the transportation of $\^$14/C did not affect at 20/10$^{\circ}C$, but it was hampered with shading at 30/20$^{\circ}C$ in both varieties.

• Journal of Korean Society of Environmental Engineers
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• v.33 no.3
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• pp.167-173
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• 2011

The Effects of external resistance on electrical properties such as current density, power density and coulombic efficiency were investigated in two-chamber type MFCs using a ferricyanide as reducing agent. A stable electricity was produced when a constant time elapsed after innoculation of mixed cultures into the anode compartment; voltages from 0.13 to 0.16 V was measured at $50{\Omega}$ of external resistance. When the external resistance was increased, the current density decreased and the power density rapidly increased and then slowly decreased. Big variation of electrical properties was observed in high-current density region due to the concentration loss related with substrate consumption in repeated experiments changing the external resistance. The maximum power density ($175.8mW/m^2$) and coulombic efficiency (46.1%) were obtained at $100{\Omega}$ of the external resistance which is nearest with the internal resistance ($134{\Omega}$) of MFC system.

• Journal of the Korean Ceramic Society
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• v.39 no.2
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• pp.120-125
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• 2002

AC powder EL devices were fabricated by screen printing method with the dielectric materials in insulating layer and the electrical resistivity of rear electrode. Brightness and current density were measured at voltage range of 50∼300 $V_{rms}$ to estimate optoelectrical properties of AC powder EL devices, respectively. Frequency generator was used as system producing frequency and voltage of a sine wave. Brightness and current density were measured by luminometer and multimeter. Also, dielectric constant for dielectric layer was measured by impedance analyser after preparing thick film. Dielectric constant was improved with amount of $TiO_2$ to $BaTiO_3$ powder. By applying such a process to dielectric layer of low cost AC powder EL device, brightness was improved to 50 cd/$m^2$ at similar current density. Dielectric constant $BaTiO_3$ powder by solution combustion process is better than commercial $BaTiO_3$ powder. By applying to that of low power consumption AC powder EL device, brightness was improved to 85 cd/$m^2$. Brightness of AC powder EL device was relatively decreased by control of electrical resistivity of rear electrode, current density was also decreased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.132-139
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• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.