• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.192.2-192.2
• /
• 2016

전기추력기는 화학식 추력기에 비해 비추력이 높아 인공위성의 자세제어, 궤도수정, 궤도천이를 포함한 행성 탐사활동 및 우주 임무수행을 위한 우주선의 엔진 등으로 다양하게 활용된다. 홀 추력기는 전기추력기 중 하나로 고리형 방전공간을 가진 고리형 추력기와 원통형 방전영역을 가진 원통형 추력기가 있으며, 원통형 추력기는 고리형에 비하여 넓은 방전공간으로 저전력 방전에 적합한 추력기이다. 또한, 저전력 추력기는 큐브셋(cubesat) 및 마이크로 위성(microsatellite)의 증가하는 수요에 따라 필요성이 증가하고 있으며, 활용도가 높아 다양하게 연구 및 개발되고 있다. 홀 추력기는 자기장과 전기장을 서로 수직되게 인가하여, 자화된 전자는 플라즈마 방전을 유지시키고 자화되지 않은 이온은 전기장 방향으로 가속되어 이온빔을 발생시킨다. 하지만, 저전력 소형 추력기는 작은 소모전력과 방전채널로 인한 성능 저하 및 자기장 구조 설계 등 많은 어려움들을 가지고 있다. 본 연구에서는, 약 50 W급의 소모전력을 바탕으로 영구자석을 이용한 저전력 플라즈마 추력기를 개발하였다. 방전 채널은 지름 15 mm, 길이 16 mm, 무게는 약 0.6 kg으로 원통형 구조의 채널로 제작되었으며, 약 1500-2000 G의 자기장 세기를 갖도록 설계하였다. 방전 기체는 제논을 사용하여 1-5 sccm영역에서 방전 특성을 살펴보았으며, 방전 전류는 0.02-0.4 A로 나타났다. 100-550 V영역에서 방전을 시도하였고, 채널길이를 16-24 mm 에서 약 1mN 급의 추력특성을 보였다. 본 발표에서, 홀 추력기의 제작 특성과 성능 및 플라즈마 특성에 대한 더 자세한 연구결과가 발표될 예정이다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.3
• /
• pp.171-183
• /
• 2018

Herein, we show the design and fabrication of a serial-to-parallel converter (SPC) using the $0.25-{\mu}m$ GaAs pHEMT process. The serial-to-parallel converter is composed of four bits to control the four phase shifters used in the core chip. The SPC stores the received serial data signal to a register in the SPC and converts the stored data into the parallel data. Each converted output data can control four phase shifters. The size of the fabricated SPC is $1,200{\times}480{\mu}m^2$ and it uses two DC power supplies of 5 V and -3 V. The consumption current of each DC power supply is 7.1 mA for 5 V, and 2.1 mA for -3 V.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.7
• /
• pp.10-16
• /
• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.26-34
• /
• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of IKEEE
• /
• v.11 no.1 s.20
• /
• pp.15-23
• /
• 2007

This paper describes a dual frequency synthesizer designed in a 0.2$\mu$m CMOS technology for wireless LAN applications. The design is focused mainly on low-power characteristics. Power dissipation is minimized especially in VCO and prescaler design. The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. It operates in the frequency range of 2.3GHz to 2.7GHz (RF) and 250MHz to 800MHz (IF) and consumes 5.14mA at 2.5GHz and 1.08mA at 0.5GHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset at IF band. The die area is 1.7mm$\times$1.7mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.1
• /
• pp.76-80
• /
• 2011

This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.275-283
• /
• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.11
• /
• pp.992-998
• /
• 2015

In case of UHF Band Transceiver for Army Aircraft, it shall follow MIL-STD-461F Figure CE101-4 most key design points for this equipment were to minize the current consumption and frequency interference since it will be integrated on aircraft. However, after design, abnomal signal(over 100 dBuA) was occured from 30 Hz to 1 kHz on CE101 test. Occured abnomal signal was measured as 50 Hz signal which was tansceiver $T_{DD}$ signal with the output power of 10 W and 20 ms periods. To meet the specification, current variation needed to be minized. Thus, $I_{dq}$ and $I_d$ of power amplifier were modified almost equally through test result and finally, the equipment was designed and developed with no difference of current consumption and frequency interference from the previous design goal.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.8A
• /
• pp.712-719
• /
• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.87-93
• /
• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.