• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.49-57
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• 2000

In this paper, lumped-element isolator is analyzed and designed using the scattering matrix approach. Using the designed parameters, compact isolator with 7.0x7.0x2.3 mm$^3$ dimensions is fabricated and tested in 1.765GHz PCS phone band. Implemented isolator shows 29.95dB isolation characteristic at center frequency and has 0.35dB insertion loss in overall 30MHz operating bandwidth. Return losses of input and output port are measured below -19 dB. Experimental results show that the implemented isolator has better performances than the conventional one.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.6
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• pp.615-620
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• 2015

This paper deals with a fault detection system design for a boiler-turbine control system of thermal power plant. We described the nonlinear properties of the boiler-turbine dynamics as a T-S fuzzy system with time varying measurable parameters. We design a residual generator using an observer based fault detection filter. In order to identify the faulted output sensor, an approximate inverse system is connected to the outport of the fault detection filter. We demonstrate the efficiency of the suggested design method via computer simulations.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.3
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• pp.316-323
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• 2004

This paper deals with an $H_{\infty}$ output feedback controller design for singularly perturbed T-S fuzzy systems. It is shown that the $H_{\infty}$ norm of the singularly perturbed T-S fuzzy system is less than ${\gamma}$ for a sufficiently small ${\varepsilon}$>0 if the $H_{\infty}$ norms of both the slow and fast subsystem are less than ${\gamma}$. Using this fact, we develop a linear matrix inequality based design method which is independent of the singular perturbation parameter ${\varepsilon}$. A numerical example is provided to demonstrate the efficacy of the proposed design method.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.189-194
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• 2006

In this paper, design of MUSIC algorithm, which is one of high resolution DOA (direction of arrival) estimation techniques was studied. Generally the complex-valued correlation matrix of MUSIC algorithm is transformed to unitary matrix or matrix expansion for the real hardware implementation. Using the orthogonality between the noise subspace eigenvectors and the steering vectors corresponding to signal component, we estimate DOA with the real-valued computation between steering vectors and noise subspace eigenvectors. The DOA algorithm was designed with VHDL models with considerations of 2 elements and 1 incident wave and its simulation results are derived.

• Journal of the Korean Institute of Intelligent Systems
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• v.27 no.1
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• pp.59-64
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• 2017

In this paper, a controller for discrete Takagi-Sugeno(T-S) fuzzy model under imperfect premise matching is proposed. Most of previous papers have obtained the stabilization condition using common quadratic Lyapunov function. However, the stabilization condition may be conservative due to the typical disadvantage of the common quadratic Lyapunov function. Hence, in order to solve this problem, we propose the stabilization condition of discrete T-S fuzzy model using fuzzy Lyapunov function. Finally, the proposed approach is verified by the simulation experiments.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.463-472
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• 2000

In this paper, we consider the problem of realizing associative memories via cellular neural network(CNN). After introducing qualitative properties of the CNN model, we formulate the synthesis of CNN that can store given binary vectors with optimal performance as a constrained optimization problem. Next, we observe that this problem's constraints can be transformed into simple inequalities involving linear matrix inequalities(LMIs). Finally, we reformulate the synthesis problem as a generalized eigenvalue problem(GEVP), which can be efficiently solved by recently developed interior point methods. Proposed method can be applied to both space varying template CNNs and space-invariant template CNNs. The validity of the proposed approach is illustrated by design examples.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.5
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• pp.914-923
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• 2002

Recently, there has been considerable interest in micro gyroscopes made of silicon chips. It can be applied to many micro-electro-mechanical systems (MEMS): devices for stabilization, general rate control, directional pointing, autopilot systems, and missile control. This paper shows how the mechanical design of the gyroscope can be done using axiomatic design, followed by the application of the Taguchi robust design method to determine the dimensions of the parts so as to accommodate the dimensional variations introduced during manufacturing. Functional requirements are defined twofold. One is that the natural frequencies should have fixed values, and the other is that the system should be robust to large tolerances. According to the Independence Axiom, design parameters are classified into a few groups. Then, the detailed design process is performed fellowing the sequence indicated by the design matrix. The dimensions of the structure are determined to have constant values fur the difference of frequencies without consideration of the tolerances. It is noted that the Taguchi concept is utilized as a unit process of the entire axiomatic approach.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.23 no.2
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• pp.163-170
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• 2011

An optimal layout condition of the offshore wind turbines is studied by using the response surface analysis which is a kind of the design of experiments. Based on the assumption that total 36 turbines would be installed in the offshore wind farm, the number and distance of the rows and columns are used as the design variables and the efficiency decrease of power generation due to the wake decay by the interactions of turbines and the installation cost of the internal electric grid are considered as the objective functions of the response surface analysis for the layout design of turbines. Useful design information can be derived by analyzing the relationship between the design variables and target functions. It is found that the row number and the distance between rows should be minimized, and the optimal distance between columns should be estimated and adopted to the layout design within the specified design range in order to ensure the economics for the offshore wind farm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.