• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Journal of the Korea Convergence Society
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• v.11 no.6
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• pp.331-339
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• 2020

The purpose of this study is to investigate the correlation and agreement between heart rates of Polar heart rate monitor and a smartwatch in order to confirm the accuracy of heart rate measured by the smartwatch. Heart rates of fifty college students were measured for a total of 12 minutes under four conditions: rest, walk, Zumba, and cycle. As a result of correlation and agreement analysis between heart rates of the two devices, correlation coefficient (r) was 0.995 at rest, 0.991 at walk, 0.923 at Zumba, 0.932 at cycle, and Bland-Altman ratio (BA ratio) was 0.02 at rest, 0.03 at walk, 0.06 at Zumba, 0.04 at cycle. Heart rate from smartwatch showed high correlation and agreement with heart rate from Polar in all conditions, representing that smartwatch can be considered an reliable apparatus to measure hear rate.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.9
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• pp.733-742
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• 2016

In recent years, gas engines fueled with LNG or synthetic gas have been attracting considerable attention for marine use owing to their potential to facilitate better fuel economy and to reduce emissions. It has been confirmed that gas engines using the Otto cycle, which involves premixed combustion, can satisfy Tier III regulations without the EGR or SCR system. The objective of this study is to acquire simulation technologies for predicting gas engine performances in industrial fields. Using the commercial software BOOST, the simulation is conducted on a gasoline engine rather than a marine engine due to the gasoline engine's easier accessibility. This study consists of two stages. In the first stage published previously, the optimal modeling techniques for representing the behavior of the gas in the intake and exhaust systems were determined. In the current study, we formulated a method to evaluate the combustion and heat transfer processes in the cylinder and to ultimately determine the major performance parameters, given that the analytical model derived from the previous stage has been applied. Through this study, we were able to determine a combustion and heat transfer model and a valve discharge coefficient that are less reliant on empirical data: we were also able to formulate a methodology through which relevant constants are decided. We confirmed that the values of transient cylinder pressure variation, indicated mean effective pressure, and air supply can be successfully predicted using our modeling techniques.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.5
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• pp.189-193
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• 2020

Recently, various methods for preparing a flexible electrode for implementing a wearable sensor have been introduced. Wearable sensors show similar tendency to use various polymer substrates, which provides elasticity suitable to the motion of human body. In this paper, a highly elastic silver nanowire based electrode was prepared on a sponge-based stretchable substrate, and electrical properties were evaluated. Silver nanowires were grown using a wet chemical synthesis, impregnated into a plasma-treated sponge, and then heat treated at a low temperature. In particular, the plasma surface treatment of the sponge enables uniform coating of silver nanowires. The flexible sponge electrode showed reliable electrical resistance changes over 160 repeated tensile-compression cycles.

• The KIPS Transactions:PartC
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• v.13C no.6 s.109
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• pp.717-724
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• 2006

This paper describes the design and implementation of architecture for convergence of home network services and data broadcasting services based on UMB and ACAP middleware; the one is used for interoperability of home networked devices, and the other for data broadcasting services. The proposed architecture provides TV-centric user interface capable of managing home network services and data broadcasting services together using a remote controller and TV sets TV applying Java TV Xlet interface and HAVi user interface for home network services like data broadcasting services. Besides, we define the service proxy for accessing home network services in a set-top box and the service broker for providing data related to home network services in a home server. Finally, the application manager in ACAP middleware manages the lifecycle of home network services through service events from the service proxy to the application manager.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.11
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• pp.1135-1140
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• 2016

The main challenge in designing wearable WBANs is to guarantee the balance of QoS demands in the network with the low power constraints of limited battery powered nodes. Low power devices implanted in or attached to the body should be designed to meet minimum energy requirements due to their limited battery life and be small in size to be easily wearable. In this paper, we propose a method for optimizing channel allocation method that is compatible with the IEEE 802.15.6 standard, enables the maximum amount of power charge at idle, guarantees the QoS of a WBAN, and provides the reliable date transmission between nodes and hubs in the network. Our extensive simulations will show that the method we propose not only maximizes the QoS in packet transmission but also improves the level of energy efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.112-117
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• 2007

This paper presents specialized DSP instructions and their hardware architecture for audio coding algorithms, such as the MPEG-2/4 Advanced Audio Coding(AAC), Dolby AC-3, MPEG-2 Backward Compatible(BC), etc. The proposed architecture is specially designed and optimized for the MDCT/IMDCT(Inverse Modified Discrete Cosine Transform), and Huffman decoding of the AAC decoding algorithm. Performance comparisons show a significant improvement compared with TMS320C62x and ASDSP21060 for the MDCT/IMDCT computation. In addition, the dedicated Huffman decoding accelerator performs decoding and preparing operand in only one cycle. The proposed DPU(Data Processing Unit) consists of 107,860 gates and achieves 150 MIPS.